Par error in Spartan-3

I met problem while doing place for Spartan-3 in ISE 7.1 .They said. Number of BUFGMUXs 2 out of 8 25% Number of External IOBs 31 out of 221 14% Number of LOCed IOBs 0 out of 31 0%

Number of Slices 9643 out of 13312 72% Number of SLICEMs 52 out of 6656 1% WARNING:Place:119 - Unable to find location. SLICEL component ins_rsa_core_combine/U_reg[768] not placed. ...... ...... ..... 0,256 ins_rsa_core_combine/U_reg[1024] ERROR:Place:120 - There were not enough sites to place all selected components

I used large width register and adder in this design, the reg will map into FF with the SLICES? And I can see SLICEM only used 52. If the silces is not enough, why the tools did not use SLICEM?

kent

Reply to
kent.mou
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I met problem while doing place for Spartan-3 in ISE 7.1 .They said. Number of BUFGMUXs 2 out of 8 25% Number of External IOBs 31 out of 221 14% Number of LOCed IOBs 0 out of 31 0%

Number of Slices 9643 out of 13312 72% Number of SLICEMs 52 out of 6656 1% WARNING:Place:119 - Unable to find location. SLICEL component ins_rsa_core_combine/U_reg[768] not placed. ...... ...... ..... 0,256 ins_rsa_core_combine/U_reg[1024] ERROR:Place:120 - There were not enough sites to place all selected components

I used large width register and adder in this design, the reg will map into FF with the SLICES? And I can see SLICEM only used 52. If the silces is not enough, why the tools did not use SLICEM?

kent

Reply to
kent.mou

Kent

I'm guessing you have a core here that is done for something like a Virtex-2. The SLICEM and SLICEL are something new in Spartan-3 where only 1 out of 2 slices can support a memory type use for LUTs in that slice. In an older Virtex2 all slices can support the memory function. So if you have a core that is a RPM or has equivalent constraints you may be trying to place a memory element where there is none and hence your error message. If it is constraints you can remove the LOC statement that causes the issue. Otherwise you are going to have to dig into the design with FPGA Editor and can edit the LOCs.

John Adair Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan3 Development Board.

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Reply to
John Adair

Hi John, Thanks a lot for your suggestion. And I tried not to add any constraints on it. But it didn't work.and It seems there are enough SLICEMs. Because it show in report and FPGA editor graph that all the SLICELS are used up, and only 1% SLCEMs are used. The par error comes from there are not enough SLICELS to place register bit. I don't konw why the tools can't place them into SLICEMS. Is there any contraints in default? And It is strange Slices number from x0 to x 72 are all SLICELS, and from X74 to X102 are half SLCIEMs and half SLCIELS. It is not the same as Spartan datasheet said. What I used is x3s1500.

Reply to
kent.mou

Maybe a carry chain that's too long ? (does the tools cut it automatically ?)

Reply to
Sylvain Munaut

Do you use local or gated clocks? In other words, does your design have FFs that are not clocked directly by the main two clocks? If so, then the limit to your design may be the amount of low skew routing for clocking, the lack of which may limit the number of usable slices for registers using different clocks.

Local and gated clocks are very useful in ASIC designs. To convert to a FPGA, you may need to convert some or all of these to using the clock enable inputs.

-- Phil Hays

Reply to
Phil Hays

The statement "Because it show in report and FPGA editor graph that all the SLICELS are used up" isn't what I saw in the lines you copied from your report. The tool should have no problem placing SliceLs in SliceM locations.

If Sylvain Munaut's though of a carry chain that's too long doesn't pan out (U_reg[768] is a lot of bits!) then opening a case with Xilinx support or contacting your FAE may be the next best step.

The resources as they're stated in the lines of the report suggest there is no raw resource problem so the issue should be specific to some aspect of your design.

Reply to
John_H

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