Field-Programmable Gate Arrays - Page 133

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• 06-12-2006
• xc3sprog -- any updates?
• • Eric
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• 12

• 
• 06-12-2006
• How do I use the DDS core in a verilog flow?
• • xilinx_user
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• 14

• 
• 06-12-2006
• Xilinx timing viloations
• • prav
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• 7

• 
• 06-11-2006
• from VHDL to FPGA
• • elesser
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• 6

• 
• 06-10-2006
• Xilinx ISE S/W Install kernel version "mismatch"
• • Rich Grise
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• 14

• 
• 06-10-2006
• initialization sequence and auto refresh for sdr-sdram
• • Subhasri krishnan
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• 9

• -
• 06-09-2006
• edk 8.1
• • cwoodring
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• 0

• 
• 06-09-2006
• Requesting for an Actel Library
• • irfan.mohammed
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• 1

• 
• 06-09-2006
• xilinx cable 3 doesn't talk with pc,but test ok
• • blisca
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• 9

• 
• 06-09-2006
• Current from FPGA pins to ADC
• • m_oylulan
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• 6

• 
• 06-09-2006
• PCI Express - Root Complex ?
• • Jerome
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• 3

• -
• 06-09-2006
• Linux 2.6 for PPC on Xilinx XUP-V2PRO board!
• • Ams
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• 0

• 
• 06-09-2006
• Good free or paid merge software that edits two similar files?
• • Weng Tianxiang
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• 15

• -
• 06-09-2006
• Jun G. Lockett assasination
• • unsaman
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• 0

• 
• 06-08-2006
• stable, tested 6502 core
• • aiiadict
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• 8

• 
• 06-08-2006
• Space invaders on Spartan3e starter board
• • MikeJ
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• 5

• 
• 06-08-2006
• Block Ram vs Distributed Ram
• • Ashish
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• 6

• 
• 06-07-2006
• Rumor Control:: Will Quartus phase out supporting AHDL?
• • jjlindula
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• 13

• 
• 06-07-2006
• Xilinx EDK: Connecting interrupt to MicroBlaze requires stdout?
• • Garrick
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• 1

• 
• 06-07-2006
• Can ILMB and DLMB of Microblaze be 24kByte?
• • Dale
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• 2

• 
• 06-07-2006
• Incrmental Compilation in Quartus 5.1
• • jjlindula
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• 3

• -
• 06-07-2006
• Xilinx SystemACE : Flash Memory
• • Henry
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• 0

• 
• 06-07-2006
• Anyone with Xilinx SP305-board ?   [ 2 ]
• • John Smith
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• 31

• 
• 06-07-2006
• Easily add 4 Gb/s Ethernet link to FPGA systems for control & data transfer
• • James Ma
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• 1

• 
• 06-07-2006
• LVTTL, LVCMOS or 3.3V-PCI?
• • kia rui
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• 2

• 
• 06-07-2006
• ICAP Virtex4 32 bits
• • Meres Five
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• 1

• -
• 06-07-2006
• SGMII with Virtex 4 embedded MAC
• • Sylvain Munaut
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• 0

• 
• 06-07-2006
• Problems with ISE logic optimization
• • dmos
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• 6

• -
• 06-07-2006
• Noise-like Vibration in Measurement Result
• • Brian
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• 0

• 
• 06-07-2006
• IOBDELAY's delay value
• • qysheng
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• 4

• 
• 06-07-2006
• API on Virtex 4 FPGA or the email of Delon Levi wanted
• • boxi.yang
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• 2

• 
• 06-06-2006
• ise8.1 picking local instead of global clk routing?
• • langwadt
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• 1

• 
• 06-06-2006
• EDK: TCL scripts in pcores directories
• • MM
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• 1

• 
• 06-06-2006
• Propagation delay sensitivity to temperature, voltage, and manufacturing
• • folnar
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• 2

• 
• 06-06-2006
• Xlinix ML403 evaluation board
• • misiu
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• 2

• 
• 06-06-2006
• GPIO problem
• • jmariano
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• 2

• 
• 06-06-2006
• ppc instruction count
• • eascheiber
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• 5

• 
• 06-06-2006
• Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
• • subint
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• 1

• 
• 06-06-2006
• ISE8.1 on OpenSUSE 64bit
• • Sean Durkin
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• 6

• 
• 06-06-2006
• Efficient implementation of Address Decoding logic
• • Srikanth BJ
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• 10

• 
• 06-06-2006
• FlipChip BGA Conformal Coating
• • bh
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• 7

• 
• 06-06-2006
• Re: Jtag Programmer
• • Colin Hankins
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• 3

• 
• 06-05-2006
• ISE Timing Analysis Misreporting? Bug?
• • Brandon Jasionowski
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• 3

• -
• 06-05-2006
• Xilinx Floorplanner basic question
• • MM
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• 0

• 
• 06-05-2006
• ProjectMgmt WARNING from ISE 8.1i XST
• • marco
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• 1

• 
• 06-05-2006
• Webpack larger than CDs
• • rickman
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• 18

• -
• 06-05-2006
• The simulation of Xilinx DDC(Digital Down Convert) IP Core can't gain the result
• • ARRON
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• 0

• -
• 06-05-2006
• Jumps in Reading out
• • Brian
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• 0

• 
• 06-05-2006
• MIL Qualified RTOS for PowerPc 405
• • Marco T.
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• 5

• 
• 06-05-2006
• Help on DDR SDRAM contoller generated by MIG1.5
• • subint
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• 5