Chipscope 7.1 and JTAG TAP

Hi,

In order to debug the basic connectivity, I would insert or instantiate a ICON/ILA or ICON/VIO and see how that works.

I've seen that 0 cores found problem when the generated core is newer than the Chipscope version.

Also, the trst_n shown is active low, is that intended for the TAP controller?

HTH,

-P@

for chipscope connection to the fpga, you need JTAG, but you can use it only when you're sure of working your JTAG controller properly. Also if you need to monitor this controller or any other design, you need to add your demanded signals to chipscope core. if a JTAG port is selected to connect to FPGA that dosn't have any apropriate core on the chip(fpga) then you will receive this report: "There are 0 Core units found in the JTAG device chain." make sure you add and generate your monitoring chipscope core to your design.

AHN

It sounds like you created your own unique JTAG TAP controller for some reason and put it in your design and expect that ChipScope would work with it. It won't.

ChipScope uses the built in JTAG controller to communicate through the internal BSCAN block and one of the internal USER ports to a soft ICON (Integrated CONtroller) core and then to 1-15 ChipScope debug cores such as ILA (Integrated Logic Analyzer) or VIO (Virtual Input/Output).

I would strongly suggest that you read the introduction chapter in the ChipScope 7.1i User Guide for a better understanding of using ChipScope.

Ed McGettigan

-- Xilinx Inc.