Field-Programmable Gate Arrays

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Xilinx Evaluation boad ISE sample project

Hello ! Does someone have verilog-HDL sample apply to Xilinx Evaluation boad [TB-4V-FX60-PRO] ? I want to sample source....
0 comments posted 18yrs
posted by life.is.dreaming
0 comments posted 18yrs posted by life.is.dreaming

Xilinx DCM outputs for DDR

Greetings, What's the best way to clock DDR flops from a DCM? In all the DDR I/O I've produced, I've always used the DC...
11 comments posted 18yrs
posted by newsgroup
11 comments posted 18yrs posted by newsgroup

multidimensional arrays in VHDL?

I am trying to covert the following Verilog code to VHDL. I am having issues with converting the arrays to VHDL. Could...
10 comments posted 18yrs
posted by thakkar.anuja
10 comments posted 18yrs posted by thakkar.anuja

Tarfessock1 - FPGA Cardbus Development Board

Images of the new version of Tarfessock1 here http://www.enterpoint.co.uk/moelbryn/tarfessock1.html. We have replaced t...
1 comments posted 18yrs
posted by g1
1 comments posted 18yrs posted by g1

How to use a generic memory with Xilinx ?

Hello all I am struggling with ISE and CoreGen to generate a memory block that would be customizable (mainly in depth &...
2 comments posted 18yrs
posted by nic_o_mat
2 comments posted 18yrs posted by nic_o_mat

Debugging EDK DDR interface

Hi all, We built a custom board with Spartan3 1200E and Quimonda 32MBx16 DDR (HYB25DC512160CF-6). The schematic is simi...
1 comments posted 18yrs
posted by ales.gorkic
1 comments posted 18yrs posted by ales.gorkic

global clock (gclk) input at xilinx virtex4 fpga

Hi there, I'm using a Virtex4 FX100 FPGA (package FF1517) in a board design and I wonder if it is enough to use just on...
2 comments posted 18yrs
posted by denkedranjoe
2 comments posted 18yrs posted by denkedranjoe

Xilinx MAC experience ?

Hi all, We are going to start a project in which we will need to use the hardware MAC Ethernet module in a Virtex 5 for...
5 comments posted 18yrs
posted by use-contact-at-www-alciom-com-for-email
5 comments posted 18yrs posted by use-contact-at-www-alciom-com-for-email

sampling error between 2 clocks

Xilinx V4SX35 ISE 8.2.03 Modelsim I got CLKI(300MHz), CLKI_DIV(150MHz) generated through a counter(just a flip_flop) cl...
23 comments posted 18yrs
posted by wxy0624
23 comments posted 18yrs posted by wxy0624

Generating a RPM in Xilinx floorplanner

Hi, I have some trouble when I try to generate a RPM using the floorplanner tool in Xilinx. I'm trying to make a RPM fr...
0 comments posted 18yrs
posted by jonlassen.news
0 comments posted 18yrs posted by jonlassen.news

[help]SAS with FPGAs

Hi,all.I am doing a project which will implement SAS with FPGAs on Xilinx Virtex 4 ML405 board. But before I am a softw...
3 comments posted 18yrs
posted by westspeed
3 comments posted 18yrs posted by westspeed

Mico32 linux kernel git repository

Hi guys, finally Mico32 linux kernel source tree is available as a git repos. Anyone interested in joining the journey...
0 comments posted 18yrs
posted by sfaragnaus
0 comments posted 18yrs posted by sfaragnaus

LVDS on Drigmorn1

In answer to all of you who asked about LVDS support on Drigmorn1 we believe 2 pairs of LVDS are very viable but as yet...
0 comments posted 18yrs
posted by g1
0 comments posted 18yrs posted by g1