I have a question regarding the T9 pin of the FT256 footprint of the spartan 3e .. GCLK0 shares pin with the RDWR_B pin which is a configuration pin whitch according to the datasheet (p.97) has to be low during configuration .. how is it possible to use GLCK0 as input for my primary fpga clock source? (im am using SPI for configuration).
If you're using SPI for configuration, you should be fine. According to the Spartan-3 Generation Configuration User Guide
the RDWR_B is only used for BPI and Slave Serial modes (table 2-15, p54 and table 2-16, p. 57).
Also keep in mind that you can use other GCLK signals as alternatives to GCLK0. Just because it's "0" doesn't mean it has to be used first. Note with the BPI mode on page 160 in the User Guide that many, many GCLK lines are taken up by that configuration mode.
You should be clean with SPI configuration; do you have functional results that suggest the data isn't accurate or was it just a matter of incompletely communicated information in the myriad of guides and tables that led you to believe you were in trouble?
Thanks for the confirmation John .. the reason i was in doubt, was that i didnt read that the mode select pins control which pins are reserved during configuration, so i assumed that all configuration pins where reserved during the configuration.