Hi all,
I am using Xilinx 9.2i schematic entry to design a simple clock circuit. The schematic uses come components that i wrote and i have added a counter from xilinx library. WHen i implement the design and fit it is ok, but when i assign package pins using PACE, i only see the inputs/outputs of the counter and not of the whole design.
The target is a Coolrunner2 CPLD.
Can someone explain to me whats happening. This is the first time i am mixing my entities with Xilinx built in components.
Thanks a lot
Joseph