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Initializing Micron DDR2 Memory

Does anyone know a way to initialize DDR2 memory models from Micron with data....easily? I have 16 DDR2 SDRAM models connected in a 2 Gigabyte SODIMM configuration. The problem I am facing is that our EDK system will eventually populate that memory with data needed during subsequent system operation.

Currently I am using C code to write data out to DDR. I am only running simulation right now, so it takes a REALLY long time to get all that data out to RAM before I use it. I know you can make .mem files that you can intitialize the RAM to using mem load commands in ModelSim. However, the crux is, since the RAM is 2GB, you can't specify the Verilog to model all that storage. If you do, ModelSim crashes...and that makes sense. The PC itself only has so much RAM to use.

So the RAM model uses some indexing style to save data into the RAM model's internal memory structure. I guess I am asking if there is an easy way to make .mem files to initialize the memory correctly.

Hope this makes some sense!

Reply to
motty
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If you post the URL from where you downloaded the models, perhaps someon will know which model you mean and be able to help you...

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Reply to
RCIngham

[snip]

Look at the MAX_MEM flag. When it is defined, the memory address just comes from addr, so the memory array can be initialized from a file. Otherwise the memory uses an indexing scheme.

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Joe Samson
Pixel Velocity
Reply to
Joseph Samson

Yeah, I can't use the MAX_MEM define. It is a 2G SODIMM and ModelSim crashes...obviously due to memory allocation.

I have to use the indexing scheme. Looking at the model's Verilog more, I don't even know if it is possible to initialize the memory when it uses that indexing scheme.

Reply to
motty

I have added my own initialization routines to the Micron SDRAM model before. I also commented out `FULL_MEM or `MAX_MEM (depending on the model) so I only had to simulate a subset of the DRAM. I used $readmemh to read a hex file into the model's storage array ("mem_array" in some models or "memory" in others). If you are spreading the memory across many models, that of course becomes more difficult. You could write an "initial" routine that uses $fscanf to read values from the file and populate the "memory" array correctly.

I wonder why you are using the model, though. If you are designing a memory controller you definitely need it. If your controller is already known to work, you don't want to use the model because it is superslow. After I designed my memory controller I couldn't tolerate the speed of it and since I knew it worked, for simulation I replaced the controller and the memory model with a few lines of code that create an array, basically like an SRAM. I also used the "bit" type in SystemVerilog to make the model, because it just uses a single bit to store one bit in the array (no X or Z). This array is monolithic so it's easy to initialize with a file. And the simulation is very fast. There is no timing information in it at all. Maybe that's what you need.

-Kevin

Reply to
Kevin Neilson

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