Field-Programmable Gate Arrays

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Spartan 3e pin question

I have a question regarding the T9 pin of the FT256 footprint of the spartan 3e .. GCLK0 shares pin with the RDWR_B pin...
2 comments posted 18yrs
posted by kislo02
2 comments posted 18yrs posted by kislo02

Newbee Microblaze system BRAM utlization confusion

Hi All , I am new to FPGA development and have learned VHDL using text books. NOW! that doesn't teach practical aspects...
10 comments posted 18yrs
posted by niladri1979
10 comments posted 18yrs posted by niladri1979

Debugging designs that are running on FPGA

Hi I have a simple question. I have a design where the RTL simulation is working. Now I would like to see if the design...
8 comments posted 18yrs
posted by Paul
8 comments posted 18yrs posted by Paul

FPGA Board design basics

Hi, I have been developing applications in Xilinx FPGAs using VHDL for the past 3 years for a small company in Virginia...
16 comments posted 18yrs
posted by poonam.murali
16 comments posted 18yrs posted by poonam.murali

Xilinx RocketIO problems

Hi. I am trying to establish a communication between two RocketIO driven Virtex2P FPGAs. I am currently simulating the...
5 comments posted 18yrs
posted by slimepit
5 comments posted 18yrs posted by slimepit

Drigmorn1 User Manual

First cut of the user manual for Drigmorn1 is now available here http://www.enterpoint.co.uk/component_replacements/Dri...
0 comments posted 18yrs
posted by g1
0 comments posted 18yrs posted by g1

I try to Tri-Mode Embedded EMAC

hello I will be trying to [Tri-Mode Embedded EMAC] except EDK tool. Can I implement only by ISE 9.1i tool ? Does anyone...
2 comments posted 18yrs
posted by yoshizu
2 comments posted 18yrs posted by yoshizu

Initializing Micron DDR2 Memory

Does anyone know a way to initialize DDR2 memory models from Micron with data....easily? I have 16 DDR2 SDRAM models co...
4 comments posted 18yrs
posted by mottoblatto
4 comments posted 18yrs posted by mottoblatto

Poor quality Xilinx boards ? Your experience ?

I just got a Digilent Spartan3E board & tried to load a bit file using webpack 9.2 IMPACT says no USB cable found. Then...
22 comments posted 18yrs
posted by rats
22 comments posted 18yrs posted by rats

Craignell and Darnaw1 Website Updates

Pictures of the new issue PGA Darnaw1 on our website http://www.enterpoint.co.uk/moelbryn/darnaw1.html. Main difference...
7 comments posted 18yrs
posted by g1
7 comments posted 18yrs posted by g1

Chipscope 7.1 and JTAG TAP

Hi I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a Instruction width of 6 bits. I have a design for whic...
3 comments posted 18yrs
posted by Paul
3 comments posted 18yrs posted by Paul

sobel in vhdl

Hi people... I am trying to find a vhdl code for 3x3 sobel algorithm to implement on a Spartan 3, FPGA. I have found ma...
4 comments posted 18yrs
posted by rossalbi
4 comments posted 18yrs posted by rossalbi