Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Help with Pmod VGA on Altera
I have a Cyclone V GX Starter kit board, with Quartus 13.1: I'd like some help on setting this up to get a Pmod VGA device to generate proper timing for VGA modes up to a 150 MHz pixel clock (1680 x...
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5 years ago
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Estimating ROM gate count in ASIC
I've searched for this but to no avail. I'd like a function f(D,W), where D=depth and W=width, which provides an estimate of the gate count of a lookup ROM implemented in ASIC gates. Yes, I know it's...
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5 years ago
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How to make Altera-Modelsim free download version to work?
Hi, I downloaded 11.0_modelsim_ase_windows.exe from Release Notes For ModelSim Altera 10.1b Apr 26 2012 Copyright 1991-2012 Mentor Graphics Corporation All rights reserved. After installing the...
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5 years ago
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How to write an "alias" statement
Hi, I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for easy reading in simulation. Here is code defining the...
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5 years ago
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Why choose a IOT smart digital lock?
Smart locks are sure to become every homeowner?s favorite. They off er the same level of security as typical mechanical door locks, but provide a range of alternatives to the mechanical key, and a...
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5 years ago
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Engineer for Xilinx Zinq in Barcelona
Contact me!! At
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5 years ago
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Periodically delayed clock
I'm preparing designs for a CPU that will be coded in Verilog on a Terasic Cyclone V GX starter kit dev board. I have a clock running at N MHz, and I have some logic that may take longer than the...
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5 years ago
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Need Information about Implementing of Modbus protocol in fpga ( mostly spartan 6)
Hello folks, I wanted to implement Modbus protocol on fpga. I don't know how to start? I read various documents on internet but didn't got any clear idea. basically my aim is to make package of this...
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5 years ago
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Simple system to manage register access in hierarchical Wishbone-connected FPGA designs.
Hi, I needed to provide convenient access to registers in an FPGA design intern ally interconnected with Wishbone/IPbus bus. There is a wonderful tool - wb gen2 in the OHWR directory, but it doesn't...
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5 years ago
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who knows how to make 480P HDMI output in VHDL code ?
code used from
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5 years ago
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New(ish) FPGA Company
I hadn't heard of this company before. They seem to be making a number of FPGA devices. Unfortunately all the docs are in Chinese. Anyone know much about them? Google can translate the web pages, but...
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5 years ago
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FPGA Market Entry Barriers
I was wondering what the barriers are to new companies marketing FPGAs. So me of the technological barriers are obvious. Designing a novel device is not so easy as the terrain is widely explored, so I...
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5 years ago
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Schematic FPGA Design on twitch
tomorrow from 20:15 cet until open end live on my channel schematic design on fpga. check it out https://www.twitch.tv/fpga_guru
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5 years ago
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Need magic incantation to prevent synthesizer misoptimisation
Hi all! I'm having a problem with the synthesis and P&R tools introducing a unnecessary gate in a critical path. Consider the following verilog: reg [31:0] mem_dataintomem = 32'd0; always @(posedge...
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5 years ago
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Strange thing, my FPGA HDMI output cannot work with cheap chinese HDMI Extender
I bought HDMI extender over optical fiber for $125, from Alibaba. HDMI Extender works well when Source is my laptop, but when source is my FPGA board,there is a problem. I enabled TMDS, HPD, DDC, 5+,...
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5 years ago
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