Field-Programmable Gate Arrays

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Help with Pmod VGA on Altera

I have a Cyclone V GX Starter kit board, with Quartus 13.1: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language...
5 comments posted 7yrs
posted by rick.c.hodgin
5 comments posted 7yrs posted by rick.c.hodgin

Estimating ROM gate count in ASIC

I've searched for this but to no avail. I'd like a function f(D,W), where D=depth and W=width, which provides an estima...
12 comments posted 7yrs
posted by kevin.neilson
12 comments posted 7yrs posted by kevin.neilson

How to write an "alias" statement

Hi, I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2...
4 comments posted 7yrs
posted by wtxwtx
4 comments posted 7yrs posted by wtxwtx

Why choose a IOT smart digital lock?

Smart locks are sure to become every homeowner?s favorite. They off er the same level of security as typical mechanical...
0 comments posted 7yrs
posted by hughjack8584
0 comments posted 7yrs posted by hughjack8584

Periodically delayed clock

I'm preparing designs for a CPU that will be coded in Verilog on a Terasic Cyclone V GX starter kit dev board. I have a...
58 comments posted 7yrs
posted by rick.c.hodgin
58 comments posted 7yrs posted by rick.c.hodgin

New(ish) FPGA Company

I hadn't heard of this company before. They seem to be making a number of FPGA devices. Unfortunately all the docs are...
17 comments posted 7yrs
posted by gnuarm.deletethisbit
17 comments posted 7yrs posted by gnuarm.deletethisbit

FPGA Market Entry Barriers

I was wondering what the barriers are to new companies marketing FPGAs. So me of the technological barriers are obvious...
57 comments posted 8yrs
posted by gnuarm.deletethisbit
57 comments posted 8yrs posted by gnuarm.deletethisbit

Schematic FPGA Design on twitch

tomorrow from 20:15 cet until open end live on my channel https://www.twitch.tv/fpga_guru schematic design on fpga. chec...
2 comments posted 8yrs
posted by olli22221
2 comments posted 8yrs posted by olli22221