I'm preparing designs for a CPU that will be coded in Verilog on a Terasic Cyclone V GX starter kit dev board.
I have a clock running at N MHz, and I have some logic that may take longer than the allotted time to complete (as N increases and the time to complete the logic each cycle decreases).
Rather than re-design my logic to use pipeline stages, I would like to do something like add a BUSY flag that would be raised when various logic units are busy, and lowered when they're no longer busy, so the clock is held before the next cycle actually triggers.
Would something as simple as this work (using an input clock, busy, busy reset, and an output clock2 that drives the system):
CLK = Cyclic N MHz clock BUSY = Asserted by various logic units when busy BRST = ~CLK CLK2 = trigger clock (on ~CLK && ~BUSY && BRST):
__ __ __ __ __ __ __ __ __ CLK __| |__| |__| |__| |__| |__| |__| |__| |__| |__ ______ BUSY ____________| |____________________________________ __ __ __ __ __ __ __ __ __ __ BRST |__| |__| |__| |__| |__| |__| |__| |__| |__|
__ __ __ __ __ __ __ __ __ CLK2 |__| |__| |________| |__| |__| |__| |__| |__| held
It would also seem I need to trigger each test to go high only on @negedge CLK so there are not partial clocks triggered, and that it would need to track @negedge BRST for going low.
Is there an easier / different way to do this?
Thank you in advance.