FPGA Market Entry Barriers

I was wondering what the barriers are to new companies marketing FPGAs. So
me of the technological barriers are obvious. Designing a novel device is
not so easy as the terrain is widely explored, so I expect any new player w
ould need to find a niche application of an unexplored technological featur
e.
Silicon Blue exploited a low power technology optimized for low cost device
s in mobile applications. They were successful enough to be bought by Latt
ice and are still in production with the product line expanded considerably
.
I believe Achronix started out with the idea of asynchronous logic. I'm no
t clear if they continue to use that or not, but it is not apparent from th
eir web site. Their target is ultra fast clock speeds enabling FPGAs in ne
w market. I don't see then showing up on FPGA vendor lists so I assume the
y are sill pretty low volume.
Tabula was based on 3D technology, but they don't appear to have lasted. I
believe they were also claiming an ability to reconfigure logic in real ti
me which sounds like a very complex technology to master. Not sure what ma
rket they were targeting.
Other than the technologies, what other barriers do new FPGA companies face
?
Rick C.
Reply to
gnuarm.deletethisbit
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torsdag den 18. oktober 2018 kl. 17.22.47 UTC+2 skrev snipped-for-privacy@gmail.c om:
Some of the technological barriers are obvious. Designing a novel device i s not so easy as the terrain is widely explored, so I expect any new player would need to find a niche application of an unexplored technological feat ure.
ces in mobile applications. They were successful enough to be bought by La ttice and are still in production with the product line expanded considerab ly.
not clear if they continue to use that or not, but it is not apparent from their web site. Their target is ultra fast clock speeds enabling FPGAs in new market. I don't see then showing up on FPGA vendor lists so I assume t hey are sill pretty low volume.
I believe they were also claiming an ability to reconfigure logic in real time which sounds like a very complex technology to master. Not sure what market they were targeting.
ce?
I'd think patents and the huge task of making the software for it
Reply to
lasselangwadtchristensen
Some of the technological barriers are obvious. Designing a novel device i s not so easy as the terrain is widely explored, so I expect any new player would need to find a niche application of an unexplored technological feat ure.
ces in mobile applications. They were successful enough to be bought by La ttice and are still in production with the product line expanded considerab ly.
not clear if they continue to use that or not, but it is not apparent from their web site. Their target is ultra fast clock speeds enabling FPGAs in new market. I don't see then showing up on FPGA vendor lists so I assume t hey are sill pretty low volume.
I believe they were also claiming an ability to reconfigure logic in real time which sounds like a very complex technology to master. Not sure what market they were targeting.
ce?
I've always wondered. So many companies have entered and then departed, le aving the duopoly. I think it must be the problem of developing the tools. As poor as they are, I think that might be the biggest impediment. Every grand new idea seems to flounder in the face of what works. Most innovati ons from Xilinx itself seem to flounder. Does anybody really use partial r econfiguration, years and years after it was introduced? All the "high-lev el" synthesis tools are either defunct or should be defunct.
Reply to
Kevin Neilson
Some of the technological barriers are obvious. Designing a novel device i s not so easy as the terrain is widely explored, so I expect any new player would need to find a niche application of an unexplored technological feat ure.
ces in mobile applications. They were successful enough to be bought by La ttice and are still in production with the product line expanded considerab ly.
not clear if they continue to use that or not, but it is not apparent from their web site. Their target is ultra fast clock speeds enabling FPGAs in new market. I don't see then showing up on FPGA vendor lists so I assume t hey are sill pretty low volume.
I believe they were also claiming an ability to reconfigure logic in real time which sounds like a very complex technology to master. Not sure what market they were targeting.
ce?
I'm not sure but I think Achronix dropped the whole asynchronous thing earl y on, making their name a minsnomer.
Reply to
Kevin Neilson
Some of the technological barriers are obvious. Designing a novel device is not so easy as the terrain is widely explored, so I expect any new play er would need to find a niche application of an unexplored technological fe ature.
vices in mobile applications. They were successful enough to be bought by Lattice and are still in production with the product line expanded consider ably.
m not clear if they continue to use that or not, but it is not apparent fro m their web site. Their target is ultra fast clock speeds enabling FPGAs i n new market. I don't see then showing up on FPGA vendor lists so I assume they are sill pretty low volume.
. I believe they were also claiming an ability to reconfigure logic in rea l time which sounds like a very complex technology to master. Not sure wha t market they were targeting.
face?
leaving the duopoly. I think it must be the problem of developing the tool s. As poor as they are, I think that might be the biggest impediment. Eve ry grand new idea seems to flounder in the face of what works. Most innova tions from Xilinx itself seem to flounder. Does anybody really use partial reconfiguration, years and years after it was introduced? All the "high-l evel" synthesis tools are either defunct or should be defunct.
I actually begged Xilinx for partial reconfiguration for many years. What they eventually offered was so crappy that I never was able to use it... pl us my need had gone by then.
No sure what you mean about "high level" synthesis. Are you talking about something above HDL? Is this graphical?
Rick C.
Reply to
gnuarm.deletethisbit
Some of the technological barriers are obvious. Designing a novel device is not so easy as the terrain is widely explored, so I expect any new play er would need to find a niche application of an unexplored technological fe ature.
vices in mobile applications. They were successful enough to be bought by Lattice and are still in production with the product line expanded consider ably.
m not clear if they continue to use that or not, but it is not apparent fro m their web site. Their target is ultra fast clock speeds enabling FPGAs i n new market. I don't see then showing up on FPGA vendor lists so I assume they are sill pretty low volume.
. I believe they were also claiming an ability to reconfigure logic in rea l time which sounds like a very complex technology to master. Not sure wha t market they were targeting.
face?
rly on, making their name a minsnomer.
I saw something that indicated they had a lot of push back from potential c ustomers so that rather than letting them get access to it they somehow enc apsulated it, but it's still there. The 1.5 GHz spec is still the same.
Rick C.
Reply to
gnuarm.deletethisbit
Tools, patents, and X and A buying up competitors I suspect.
Both are getting used in the push for FPGAs to become cloud accelerators (eg Microsoft, Amazon, Intel). The application code (defined by some middleware, eg OpenCL) is HLSed into some block which is partially-reconfigured into an FPGA that's in the server running the cloud app(s). The outer ring of the FPGA (memory controllers, networking, PCIe, etc) stays the same, and different apps are partially reconfigured in and out. Linux now has kernel support for this.
Theo
Reply to
Theo
s. Some of the technological barriers are obvious. Designing a novel devi ce is not so easy as the terrain is widely explored, so I expect any new pl ayer would need to find a niche application of an unexplored technological feature.
devices in mobile applications. They were successful enough to be bought b y Lattice and are still in production with the product line expanded consid erably.
I'm not clear if they continue to use that or not, but it is not apparent f rom their web site. Their target is ultra fast clock speeds enabling FPGAs in new market. I don't see then showing up on FPGA vendor lists so I assu me they are sill pretty low volume.
ed. I believe they were also claiming an ability to reconfigure logic in r eal time which sounds like a very complex technology to master. Not sure w hat market they were targeting.
s face?
, leaving the duopoly. I think it must be the problem of developing the to ols. As poor as they are, I think that might be the biggest impediment. E very grand new idea seems to flounder in the face of what works. Most inno vations from Xilinx itself seem to flounder. Does anybody really use parti al reconfiguration, years and years after it was introduced? All the "high -level" synthesis tools are either defunct or should be defunct.
t they eventually offered was so crappy that I never was able to use it... plus my need had gone by then.
t something above HDL? Is this graphical?
I put "high level" in quotes because most of the high-level tools end up be ing very non-abstract if you actually want to meet timing. I'm talking abo ut all the Matlab-to-gates, C-to-gates, and graphical tools like System Gen erator, etc. None have ever panned out. And even HDL still has to be used at a pretty low level.
There was also hardware-in-the-loop simulation (for example, using System G enerator) and I don't know if that's still used by anybody or not.
Reply to
Kevin Neilson
The industry is certainly worse off because of the lack of competition. Xilinx makes good technology, but their front end is simply awful. EDA is hard. Trying to keep the "sell the hardware, give away the tools" mentality has led the industry to accept an astonishly bad "situation normal" solution. The echo chamber of these in house developer's conversations must be deafening.
The amount of money and personel spent on developing in-house "free" EDA, is likely staggering. And the hope of these "high-level" tools being solved by a semiconductor vendor now when the entire EDA industry has been attempting (and failing) to solve this problem for over 20 years? Nil.
The industry really needs more competion in this arena. Will it happen with the two patent gorillas in the room? I don't see much...
Regards,
Mark
Reply to
gtwrek
Some of the technological barriers are obvious. Designing a novel device i s not so easy as the terrain is widely explored, so I expect any new player would need to find a niche application of an unexplored technological feat ure.
ces in mobile applications. They were successful enough to be bought by La ttice and are still in production with the product line expanded considerab ly.
not clear if they continue to use that or not, but it is not apparent from their web site. Their target is ultra fast clock speeds enabling FPGAs in new market. I don't see then showing up on FPGA vendor lists so I assume t hey are sill pretty low volume.
I believe they were also claiming an ability to reconfigure logic in real time which sounds like a very complex technology to master. Not sure what market they were targeting.
ce?
I put a little more thought into this: what if I wanted to start an FPGA c ompany? I could try to find an innovation or new niche, but that usually f ails, partly because people don't want to migrate to something new. I sure don't.
Say I want to make regular FPGA. First I have to make the silicon, which i s hard, but let's assume I use a regular architecture with 6-input LUTs and maybe some block RAMs and DSP multipliers. No processor cores or anything . I wouldn't want to try to make my own simulator. I know FPGA companies try to make their own so customers can get a cheap version but I'd try to a void that. I'd also farm out the synthesis as much as possible. I'd get S ynplify to do that. I still have to make the place & route tool and timing analysis tools unless I can find somebody who is already doing that and ca n just have them adopt my architecture.
So now I have a pretty standard FPGA, and maybe some tools, but I still hav e to compete with the established duopoly and their marketing and distribut ion networks. Could I compete on price? I doubt it. I'm not sure anybody has a compelling reason to switch to me.
Reply to
Kevin Neilson
Some of the technological barriers are obvious. Designing a novel device is not so easy as the terrain is widely explored, so I expect any new play er would need to find a niche application of an unexplored technological fe ature.
vices in mobile applications. They were successful enough to be bought by Lattice and are still in production with the product line expanded consider ably.
m not clear if they continue to use that or not, but it is not apparent fro m their web site. Their target is ultra fast clock speeds enabling FPGAs i n new market. I don't see then showing up on FPGA vendor lists so I assume they are sill pretty low volume.
. I believe they were also claiming an ability to reconfigure logic in rea l time which sounds like a very complex technology to master. Not sure wha t market they were targeting.
face?
company? I could try to find an innovation or new niche, but that usually fails, partly because people don't want to migrate to something new. I su re don't.
is hard, but let's assume I use a regular architecture with 6-input LUTs a nd maybe some block RAMs and DSP multipliers. No processor cores or anythi ng. I wouldn't want to try to make my own simulator. I know FPGA companie s try to make their own so customers can get a cheap version but I'd try to avoid that. I'd also farm out the synthesis as much as possible. I'd get Synplify to do that. I still have to make the place & route tool and timi ng analysis tools unless I can find somebody who is already doing that and can just have them adopt my architecture.
ave to compete with the established duopoly and their marketing and distrib ution networks. Could I compete on price? I doubt it. I'm not sure anybo dy has a compelling reason to switch to me.
Yes, with the approach you describe, being the new, mediocre FPGA company, success is anything but assured.
I think the given is that there has to be something different about your de vices or at least your approach. I donn't know if the Silicon Blue devices are as much different technologically or if they simply used conventional features with a different focus. I do know that when Lattice took them ove r they bent the - still in final development - iCE40 devices back toward th e mainstream with higher speeds and losing a bit on the low static power. Not a big change, but interesting none the less.
Rick C.
Reply to
gnuarm.deletethisbit
..snip
Yes of course, why do you think companies like Xilinx spend so much money on developing it? Is it to make sure their developers are not getting bored, they have money to burn or is it simply because their high-end customers (clearly not you) require it? If you work on a complex bit of IP which required physical synthesis, hand placement etc to meet timing wouldn't you want a way to preserve it? Do you think companies will simply re-synthesize, P&R and re-validate the whole design (or IP block) again after making a small change?
All the "high-level" synthesis tools are either defunct or should be defunct.
Why should be defunct? Playing with Flipflops, shift registers, luts etc is nothing more than assembly for programmable logic. There is nothing more painful to discovered that your carefully hand-crafted RTL design which you spend many man-years of effort on requires and extra pipeline stage or you need to reduce resources as you are over resourced. Wouldn't it be nice if you could write your design in sequential untimed code and use a tool to generate the architecture for you based on resource and timing constraints? There are some very successful HLS tools (CatapultC, Stratus, Synphony) but given their price they are mainly used by high-end companies (the so called 20%). Xilinx's Vivado HLS is the exception as it is quite affordable but from what I understand not as capable as the others. Yes I know it still requires tweaking and FPGA/ASIC know-how but these tools are in full production for many years and are used successfully by many companies. More and more EDA supplier are starting to offer these tools, they can't be all wrong, right?
Hans.
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Reply to
HT-Lab
Well, yes, it would be nice if such a tool existed. It doesn't. If it did, people wouldn't be paying me to make hand-pipelined designs. People wouldn't pay me to spend two months doing what I can model in Matlab in two lines of code.
Reply to
Kevin Neilson
s. Some of the technological barriers are obvious. Designing a novel devi ce is not so easy as the terrain is widely explored, so I expect any new pl ayer would need to find a niche application of an unexplored technological feature.
devices in mobile applications. They were successful enough to be bought b y Lattice and are still in production with the product line expanded consid erably.
I'm not clear if they continue to use that or not, but it is not apparent f rom their web site. Their target is ultra fast clock speeds enabling FPGAs in new market. I don't see then showing up on FPGA vendor lists so I assu me they are sill pretty low volume.
ed. I believe they were also claiming an ability to reconfigure logic in r eal time which sounds like a very complex technology to master. Not sure w hat market they were targeting.
s face?
GA company? I could try to find an innovation or new niche, but that usual ly fails, partly because people don't want to migrate to something new. I sure don't.
ch is hard, but let's assume I use a regular architecture with 6-input LUTs and maybe some block RAMs and DSP multipliers. No processor cores or anyt hing. I wouldn't want to try to make my own simulator. I know FPGA compan ies try to make their own so customers can get a cheap version but I'd try to avoid that. I'd also farm out the synthesis as much as possible. I'd g et Synplify to do that. I still have to make the place & route tool and ti ming analysis tools unless I can find somebody who is already doing that an d can just have them adopt my architecture.
have to compete with the established duopoly and their marketing and distr ibution networks. Could I compete on price? I doubt it. I'm not sure any body has a compelling reason to switch to me.
, success is anything but assured.
devices or at least your approach. I donn't know if the Silicon Blue devic es are as much different technologically or if they simply used conventiona l features with a different focus. I do know that when Lattice took them o ver they bent the - still in final development - iCE40 devices back toward the mainstream with higher speeds and losing a bit on the low static power. Not a big change, but interesting none the less.
For some satellite work I used the Microsemi RTAX, which filled a niche for rad-hard designs. It was slow, had few gates, could only be burned once, and had poor tools, but still had a small market. They made up for low vol ume with high prices. I think they're still around. Since I work with a l ot of Galois arithmetic, one thing I'd like to see is an FPGA with special structures for Galois matrix multipliers (instead of, say, DSP48s) and matr ix transposers, but I don't think the demand is enough to warrant a special architecture.
Reply to
Kevin Neilson
Microsemi is still around (though part of Microchip now). They have a number of FPGA families, that are somewhat distinct from the big two.
Reply to
Richard Damon
for rad-hard designs. It was slow, had few gates, could only be burned on ce, and had poor tools, but still had a small market. They made up for low volume with high prices. I think they're still around. Since I work with a lot of Galois arithmetic, one thing I'd like to see is an FPGA with spec ial structures for Galois matrix multipliers (instead of, say, DSP48s) and matrix transposers, but I don't think the demand is enough to warrant a spe cial architecture.
I've never found the Actel devices to be a good solution for any of my prob lems. Mostly they follow the same path that the big two follow regarding p ackages, namely larger, more pins and more dollars that optimal for my desi gns. I find Lattice is the only company that has much in the smaller packa ges with a low enough price.
I wonder what Microchip will do with the FPGA product line now. I see they have Atmel's CPLD/SPLD line as well as the rather obsolete AT40K products, but nothing of the Actel devices. I guess they are presently running Micr osemi as a separate company for now.
Rick C.
Reply to
gnuarm.deletethisbit
I think Achronix is embedded FPGAs only at this point.
I spoke with an ex-Achronix guy a few years ago in a conference. He was confident that Tabula never had their mystical reconfiguring tech working and that the whole company was a scam. He basically said they are good with muxes and suck with random logic. Tabula was at the conference demonstrating some kind of ethernet switch which would be mostly muxes... No idea if he was right or wrong. He was expecting Achronix to go under too. Tabula closed in 2015 and apparently Altera hired some of the team and maybe some of Tabula's IP. But I don't see them putting out anything resembling what Tabula claimed to have.
Really the question is, how much better than Xilinx or Intel would you need to be to break into the market? You'd probably need a billionaire who'd want to disrupt the market. Musk and Tesla come to mind. Other possibility I can think of is state funded efforts from China, I think I read they've increased funding for hardware research considerably.
I remember an interview with a Flex Logix founder, they do embedded FPGAs only. He basically said he had no interest in trying to compete with the two giants and so he found a niche. The niche may have grown, Achronix is there too and I think I heard old timer QuickLogic also plays in that business now. Probably some other startups too.
Come to think of it, it would be interesting to know what companies and what chips actually integrate FPGAs and do they farm out the design work? Or is it the embedded FPGA provider who does the design work for the programmable part?
Reply to
Anssi Saari
face?
Yes, I guess embedded PIP (Programmable Intellectual Property) is a niche. I think there are other niches. Lattice found (or bought a company who fo und) a niche for low power, small FPGAs. I expect there are others. Or yo u can market devices differently. I suppose X and A know where their bread is buttered, but I have always felt that FPGAs were underexploited and cou ld very easily be used like MCUs if they were marketed like MCUs. Lots of flavors in lots of packages. Xilinx has always acted like it can't afford to produce a wider range of packages. 10,000 LUTs is still a small chip. Give it as many I/Os as a 48 pin QFP will support and I think it will be ab le to do a lot more than MCUs. Some people think the propeller is great, b ut you could have 30, 40 or even 50 small soft-cores in a small FPGA all wo rking independently.
Having all the work done by the FPGA provider would limit the number of app lications.
Rick C.
Reply to
gnuarm.deletethisbit
It does. If you ever visit DVCon, DAC, DATE etc go to the Mentor/Synopsys/Cadence/Xilinx stand and tell them you are interested in architectural exploration using untimed C/C++ code.
If it did, people wouldn't be paying me to make hand-pipelined designs.
What about a) your clients are not willing to change their design to untimed C/C++ code? b) it is cheaper to pay a contractor for 2 month than it is to pay $100K+ for an HLS tool?
People wouldn't pay me to spend two months doing what I can model in Matlab in two lines of code.
I do hope you are not working for Xilinx as they will call you in for a mandatory training session on Vivado's HLS :-)
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After watching this consider what a top of the range HLS tool can do.
Hans
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Reply to
HT-Lab
Niches have to be large enough to allow the costs of the masks and engineering to be recovered.
The use of open source tools let the ICE40 be used in applications such as Raspberry Pi "hats", but the 8Kluts limit is restricting this niche.
Some hobbyists long for DIP packages and 5V i/o. Though this is a tiny niche, using an obsolete node (like 250nm or 350nm) might make crowdfunding practical. It would probably be more popular than
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About SiliconBlue, part of their motivation were the expiration of a bunch of FPGA patents. Even more have expired since then.
-- Jecel
Reply to
Jecel

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