Hi all!
I'm having a problem with the synthesis and P&R tools introducing a unnecessary gate in a critical path. Consider the following verilog:
reg [31:0] mem_dataintomem = 32'd0;
always @(posedge CLK) begin if (mcu_active && (w_we_recv || w_tlb_recv)) mem_dataintomem
If the synthesizer is using a simple template approach to generating the reset and clock control signal, it would probably be best to code your logic the way the template expects it, typically:
always @ (posedge clk) if (reset condition) reset actions else if (enable condition) enable actions
Logically this is the same as what you've written, but the template fits the expectations of the synthesizer better.
Okay, I figured it out. The flip-flop is behaving differently than my expectations.
Specifically, I had assumed the synchronous reset is fully independent and will have its effect if it is independently asserted during the clock edge. In actual fact, iCE40's synchronous reset only takes effect if the clock_enable is also asserted. So, to reset the flip-flop, you have to assert BOTH reset and clock_enable.
Therefore, the extra wire.
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