Help with Pmod VGA on Altera

I have a Cyclone V GX Starter kit board, with Quartus 13.1:
formatting link

I'd like some help on setting this up to get a Pmod VGA device
to generate proper timing for VGA modes up to a 150 MHz pixel
clock (1680 x 1050).
The Pmod VGA device:
formatting link

It has 4-bits each for R,G,B, and 2-bits for hsync and vsync.
The timings for VGA video modes can be found here, along with
the polarity of the hysync and vsync signals:
formatting link

My primary goals are to support these modes and to get my VGA
monitor to recognize the signal:
640 x 480
800 x 600
1024 x 768
1280 x 1024
1680 x 1050
I'm content to draw alternating red, green, blue bars of about
16 pixels each, interspaced with black and white squares. Just
something to show an image.
My goal is to get two of these devices working simultaneously
on the FPGA, and to setup the ability to read RAM for the pixels.
I wouldn't even mind supporting a monochrome output for now to
be honest. I just want to be get the displays up and running
and I can add-on from there.
-----
Would anyone like to help me with this project? I'm looking for
someone to help me with the Verilog code, and to go through the
steps in Quartus to get it to synthesize and update the FPGA. I
don't have test equipment, so if someone can use their test equip-
ment to help me in that area it would be appreciated too. I fig-
ure we can share code. I'll write what I think it should be (I
already have it written), and someone can help guide me where I
am wrong, or where the idea / design is incomplete. Plus, all of
the aspects of getting it to work with an FPGA.
The GX Starter Kit also has a built-in HDMI if someone would like
to help me with that instead.
Thank you in advance.
--
Rick C. Hodgin
Reply to
Rick C. Hodgin
Loading thread data ...
=830
]>I'm looking for someone to help me with the Verilog code, and to go throu gh the steps in Quartus to get it to synthesize and update the FPGA.
The Cyclone V GX Starter kit has an installed demo using the HDMI port. Its Verilog source code is at Terasic. Edit source code until you get what yo u want (e.g. incremental development). However, there is a lot of source c ode to examine.
The Digilent Pmod VGA device has VHDL source code demo and timings for diff erent rasters. However the GX Starter kit does not have Pmod connectors so one must use jumper wires to connect the Starter kit to the VGA Pmod board . And edit the pin constraints to match.
At a more basic level there are Altera/Intel tutorials:
formatting link
Suspect that this is where you need to start?
Reply to
jim.brakefield
ough the steps in Quartus to get it to synthesize and update the FPGA.
ts Verilog source code is at Terasic. Edit source code until you get what you want (e.g. incremental development). However, there is a lot of source code to examine.
Can you point me to a link. I saw the video on YouTube that they went thro ugh, but it involved a lot of little comments about things that I didn't un derstand. They are tool-related, and design-implementation-in-FPGA related . I could really use someone to take me through the process and help me un derstand what's required of the tool to make it work.
fferent rasters. However the GX Starter kit does not have Pmod connectors so one must use jumper wires to connect the Starter kit to the VGA Pmod boa rd. And edit the pin constraints to match.
I can try. I think I need help using the tool. It's difficult for me to e nter into new tools and other ways of thinking due to dyslexia and the diff iculties I have in reading certain types of technology books / tutorials / etc.
--
Rick C. Hodgin
Reply to
Rick C. Hodgin
Sample code for doing VGA with simple I/O:
formatting link

The support page of the board you linked to has resources including an HDMI demo:
formatting link

For using the tools, the old Altera website had great instructional videos. This seems to be the new Intel branded page:
formatting link

Good luck!
Reply to
Emilian Miron
MI demo:
s. This seems to be the new Intel branded page:
Thank you, Emilian. I will check them out. I've looked at the videos befo re, and I'm still not sure I get it. I think I need someone to help me ove r TeamViewer + voice chat or something. Just enough to answer what are som e probably very basic questions, but they are show-stoppers / blockers for me today.
In the meantime...
A friend of mine has me working on a Scott CPU emulator at present. My des ign has a built-in single-step debugger, and emulates the Scott CPU from th e book "But How Do It Know?" by J. Clark Scott. That CPU is a real, functi onal, simple 8-bit CPU with less than 40 instructions encoding about 220 si ngle-byte opcodes with variations, limited I/O, and uses 256 bytes of RAM:
formatting link

This person is a professional CPU designer since the 70s, and he wants me t o complete my work and send him a copy of my code and design. He said he'd do the same and then send me his copy. We'd look them over and compare no tes with our approaches, designs, thoughts, extensions, how we implemented various things, etc.
I think he's using it as a teaching tool because he's told me how he design s things on paper and in emulators rather than in hardware. He came up wit h this design after I told him I was devoting development time to my Logici an tool. I think he's worried about me. :-) But, I can already design and write emulators. I'm looking now to move my designs into real hardware.
--
Rick C. Hodgin
Reply to
Rick C. Hodgin
esign has a built-in single-step debugger, and emulates the Scott CPU from the book "But How Do It Know?" by J. Clark Scott. That CPU is a real, func tional, simple 8-bit CPU with less than 40 instructions encoding about 220 single-byte opcodes with variations, limited I/O, and uses 256 bytes of RAM :
If anyone's interested, here's the project:
formatting link
/emulator
formatting link

To build and test it: c:\> git clone
formatting link
Cloning into libsf... c:\> cd hardware\scottcpu\emulator\ c:\hardware\scottcpu\emulator\> dir *.*
You can load the emulator.sln file in Visual Studio 2008 or later. Load th e Debug build profile. Rebuild and press F5 to run. In the emulator:
F10: Single step F5: Run F2: Toggle I/O registers F3: Toggle GP registers F4: Toggle Output/RAM Ctrl+F5: Reset
You can also arrow around and input hex values only. If interested, Please report any bugs. It may lock up if you press F5 and your program doesn't have a termination point. Haven't tested that yet. It will also lock up i f it doesn't terminate on a JMP self instruction, like:
@@: jmp @b
--
Rick C. Hodgin
Reply to
Rick C. Hodgin

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.