4 years ago
I needed to provide convenient access to registers in an FPGA design intern
ally interconnected with Wishbone/IPbus bus. There is a wonderful tool - wb
gen2 in the OHWR directory, but it doesn't support nested slaves neither ve
ctors of registers. Therefore, I've decided to prepare a similar tool, base
d on wbgen2 concept, but written in Python.
The first version is already available in
and is available under GPL v2 license.
The solution is oriented on control applications not on high-traffic data t
ransfer. Therefore, it supports onle classic mode single accesses.
Please note, that the code was written just in a few days, so it is not wel
l structured. However, I hope that it may be usefull for others. I'll appre
ciate any remarks, suggestions of improvements or bug fixes.
With best regards,