PLL tricks

It won't multiply the jitter. The phase noise goes up because the period goes down, so a given number of picoseconds amounts to more radians.

Cheers

Phil Hobbs

A) My entire jitter budget is not 1 ps

B) Random jitter adds as the square root of the summed squares, not linearly.

I've seen that. I'd have to convert the phase noise curve to jitter. If I had a 10 Hz loop, I'd be running at the -73 dB point, whatever that means. Their fs jitter spec is (probably?) cycle to cycle.

But I should investigate further. Thanks.

Fox and SciLabs make tiny surface-mount synthesized (any frequency you want) VCXOs with PECL outputs and claimed sub-ps RMS jitter. The question is, over what time span is the jitter that low?

That is RMS, I was quoting peak (max). See above in the text you quoted...

The 10EP52 data sheet is available online, at OnSemi.

The RMS jitter is specified as 200 fs typ, and the RMS jitter is specified as 1 ps RMS max.

"Peak jitter" has no meaning.

Ok, so just the two FFs in your circuit create 1.4 ps of jitter RMS "max" then, no?

If you ask, they will probably tell you.

You aren't interested in longer periods, because eventually you are going u se their voltage input to lock the frequency to the 10MHz reference which y ou are given as part of your site services, and to which you are obliged to lock your 155.52MHz frequency source.

The time constant around the phase-locked loop that eventually locks your 1

In fact the obvious SciLab part

will give you anything from 10 to 945MHz and selected outputs up to 1.4GHz.

If you wanted something to divide down to 10MHz and 155.52MHz, choosing 933 .12MHz and feeding it into a pair of AD9915's - as an external reference cl ock - might be a neat solution. A value of 1.9968GHz is just inside the 1.4 GHz limit, and quite close to an exact multiple of 10MHz.

No. They are inside the PLL feedback loop.

You might consider moving over to the "basics" newsgroup. It gets timesome explaining this simple of stuff to newbies.

I know, it is hard to explain something you don't understand.

How can a very slow PLL reduce the cycle to cycle jitter of the PD?

is.

from LC

filter

on

of 1

LC

My bad on switching dimensions incorrectly. I think my question still applies to tempco.

?-)

Unlikely. The 1 PPS copes out of the GPS chipset directly and has some pretty interesting specifications. Look them up some time.

?-)

Yes, John Larkin gets the prize for the most interesting project of the week. Lucky dog.

Here's a possible idea for evaluating the feasibility of different schemes. Calculate the entropy of the 155.52 MHz signal. Estimate the frequency drift of the VCXO and represent it as the number of bits of information lost per 12.5 us update period. Then the feedback needs to supply at least this number of bits of information to be a possible solution. If the required feedback SNR is too high, then you know you need to use the information from more phase comparisons, not just the easy 12.5 us ones.

ChesterW

Not exactly lucky. He sold the same mob quite a lot of hardware when they f irst set up their 192 precisely synchronised lasers.

He's been carving a niche for himself in that kind of high-speed gear for q uite some time now. Interesting that he doesn't seem to know as much about it as Phil Hobbs and Keven Alyward, who haven't. Getting stuff to work does seem to steal time from thinking about how it works.

On a sunny day (Tue, 16 Sep 2014 00:39:45 +0200) it happened Gerhard Hoffmann wrote in :

That is is true, but even then I found these JFET oscilators are very stable and noise free. You can use those in parallel too:

This may fall in the category of grandmothers and eggs, but here goes:

The GPS module will have a local clock in the few tens of MHz range. One that I know about had to put the 1PPS edge on one of its local clock edges, instead of exactly at the start of the second. For high precision, you have to take this into account. The one I used could tell you (via its serial port) the offset between the most recent 1PPS pulse and when the second actually started, so you can apply a correction. This had to happen for every single 1PPS edge.

It's entirely possible that the GPS module you have can send the 1PPS exactly on time, but it might be worth checking.

Matt Roberds

Absolutely. it's not a counter. it's an accumulator, what you need is overflow on adding that perform the modulus operation. I can think of a coule of different ways to fake that by adding extra "add" steps, or using different step sizes based on a value comparitor (like the overflow flag)

However if you've got enough memory for a full wave table (and aren't using cordic or some other computational method) you could store the values in the order encountered at your desired step size (if you only want a single step size) and then, as you propose) use a counter with a limit reset.

The jitter has some (very wide) intrinsic frequency spectrum, which will get folded (aliased) a zillion times into the fundamental interval, and will therefore be very nearly white, apart from possible power supply problems.

The loop bandwidth will probably be only a few hundred hertz, because you have to filter out the gross ugly ripple from the bang-bang PD without making the loop unstable. Say 200 clocks at 80 kHz.

Most of the DFF's jitter will thus get filtered out.

Cheers

Phil Hobbs

So you think that there should be a tempco of some forcing function? What does that mean?

How would you calculate the phase tempco of a filter?

Cheers

Phil Hobbs