PLL tricks

The difference is that the output of the PD can have jitter and it has very little effect on the result. I don't know how much jitter and delay will be introduced by the reclocking FF, but it directly impacts the sampling by the PD which is what John seems to want to minimize.

John acknowledges that the reference will have jitter and arbitrary delay. So I suppose none of this matters much.

Ok, so how much does the resync FF add to the jitter? It seems there is no concern with the actual delay, just the jitter.

I'd guess that the FPGA divide-by-1944 might have 5 or 10 ps RMS jitter, and will have a ghastly TC, 10s of ps per degree C. The ECL resync flop cleans all that up.

That doesn't answer the question. How much jitter does the resynch FF add to the VCXO clock jitter? Do you have a number or at least an order of magnitude?

I don't think so. I think by that time they'd learned their lesson:

(sorry, couldn't find a free video)

Have you considered Ethernet/AVB or perhaps the 802.1AS subset?

You have to divide with _something_, and it would be hard for a part with a 300 ps propagation delay and subpicosecond decision time to introduce much.

Cheers

Phil Hobbs

It's elegant, but it seems counter-intuitive that the rather tough specs can be met when throwing away over 99% of the phase comparison information (1-1/125).

ChesterW

If you can get by with a synchronously-tuned BPF, which you probably can, you could run a very slow delay-locked loop comparing the 10 MHz with itself, before and after the filter, perhaps with another ECL DFF. Tune a varactor or two with the output of that. It'd cost $15 or so for another DFF and a couple of comparators, but that's a lot easier than doing it with N750s.

Since the forcing would be very slow, you could run the loop intermittently to save jitter in the intervals you really care about.

Cheers

Phil Hobbs

For a constant loop bandwidth, you should get some noise averaging by doing the phase comparison faster, I agree. However, since you have to crank down the BW to filter out the gross amounts of ripple from a bang-bang phase detector, I expect that it won't be that different inside the BW.

Of course, losing all that loop bandwidth does mean that the VCXO has to be a lot better than it would with a 10 MHz comparison frequency.

Using local feedback, i.e. a DDS-based or fractional-N loop (wide loop BW but probably fairly horrible drift) inside an 80-kHz bang-bang loop would relax the requirements on the VCXO proper.

This is all such fun that I may have to try building something like that.

Cheers

Phil Hobbs

Interesting, thanks.

Cheers

Phil Hobbs

The MC10EP52 has a data sheet typical random jitter of 200 fs RMS, 1 ps max. I can't measure that low. Our best scope is about 1.5 ps RMS.

Am 15.09.2014 um 20:29 schrieb John Larkin:

points if it is well behaved. So, a really low working Q helps.

Probably it will turn out to be hipass/lowpass with corners in due distance from 10 MHz. Multiple poles are probably not so desastrous then, but at 10 MHz the Hi/Lo-passes must be as flat as can be.

Also, I see that the 1pps goes directly into the high speed compartment in the block diagramm. 1pps out of a GPS receiver is usually just a port bit of the CPU. It is precise only if you can average many of these pulses. If you are lucky there is a register in the GPS where you can see how far off it was, after the fact.

Cheers, Gerhard

(excellent, that Rioja!)

Yes, this is for NIF. Some years back, we designed the VME modules that receive the OC3 fiberoptic master timing signals and fire devices all over the facility. We phase-lock a 155.52 MHz XO to the data stream, and decode timing packets.

Now I'm looking into building the other end, the data generator.

I'd love to buy a 155.52 MHz VCXO that has really low jitter. I have a

I almost never do. Bipolars are much more predictable.

This Mr. Driscoll of Northrop/Grumman is the one with the Driscoll oscillator. It is highly rewarding to read his publications.

regards, Gerhard

Den tirsdag den 16. september 2014 00.26.41 UTC+2 skrev John Larkin:

first hit on google,

-Lasse

John,

a recent posting on the Time Nuts mailing list mentioned a GHz range VCXO (with what seems a rather complex internal multiplier and filter structure) that's supposed to have noise in the picosecond range.

There are some phase noise graphs, but it's far out of my range of experience to interpret them, so this thing may be in the ballpark of what you are looking for - or it it may not.

The pulling range is +/- 50 kHz @ 1GHz nominal and the range of available nominal frequencies is from 800 MHz to 1.2 GHz. Two frequencies in that range that will divide exactly to 155.52 MHz (x6 and x7), many more will with a fractional PLL.

The module looks decidedly non-cheap (at least from appearance, no idea what it really costs), but who knows, if might be worth an inquiry.

Regards Dimitrij

I don't think so. I think the point that was being made was that most DDS chips have a fixed binary modulus or 2^32 or 2^48 or whatever, so that you can't get an exact frequency match to any number that isn't a power of two.

In general the modulus doesn't have to be fixed, let alone a power of two, and - for example - the AD9915 has an arrangement that lets you set up pretty much any modulus you want. If you are rolling your own DDS you do have the same freedom.

Can you get an AT cut 17.28 MHz xtal (maybe in an oven?) and multiply it by

Also, I have seen Rubidium clock oscillators that have a DDS output that is user selectable. I wonder if it would be clean enough?