PLL tricks

You could try the idea by separating the paralleled amplifier outputs into two groups using your existing board.

ChesterW

But then I still had to build another copy of the other gain stages. Maybe I'll do a "stereo" version with all switches under software control and less gain per stage since I have 1 dB gain missing at

Also, everything seems to have a lot of 1/f noise, so the effort to extend the coupling to 0.1 Hz is somehow wasted. since the measurements are under program control, I could just as well live with a 10 Hz lower edge frequency and compute the pole away. That would give more dynamic range, not less in praxi.

The NIST people have used correlation and get 10 dB deeper into the noise, but the 20 averaged opamps bring me quite close. I'm sorry that I have given away the other unpopulated boards. The

All my Pb batteries are sulfated, the perfect insulator. :-( Not one uA charge current at 35V. I won't buy new ones, ever. There is the starter battery of my R1200GSA bike however, lets see.

Lithiumferrophosphate seems to be more interesting.

Gerhard

my R1200GSA bike however, lets see.

Your bike is a famous movie star.

ChesterW

The producer didn't have the special-effects budget.

The problem is imaginary. Reclocking the divider output from the VCXO gets rid of all the divider junk, and the resynchronized output has the same jitter as the VCXO, plus whatever very small contribution comes from the D-flop. If it existed, a DFF with a clock enable would function in much the same way. What difference do you see between the two cases? The DFF output is synchronous with the VCXO either way.

Cables and distribution systems will have to be calibrated somehow, but that's not the problem at hand.

Cheers

Phil Hobbs

From the VCXO.

Cheers

Phil Hobbs

The cross-spectrum trick can also be extended to more amplifiers. With N of them, you get N(N-1)/2 cross spectra, which allows better noise rejection. It's only really practical at low speed, unless you have a lot of hardware, but 10 amps and 10 T/H stages will get you another 17 dB or something like that.

Cheers

Phil Hobbs

IMHO you don't need to implement the entire counter in BCD. All you need is a binary counter + a simple compare/reset circuit to reset the counter after 10e6 steps. The representation should have no influence on the operating principle. Am I wrong?

Best regards, Piotr

I did mention that somewhere. Ultimately I have to send out fiberoptic data frames that include time-of-day fields. The GPS box gives me 10 MHz and 1 PPS references, and an occasional Ethernet message will give me time to within 1 second. The FPGA contains the counters and logic and stuff, and a uP manages things at the millisecond level. The whold project is pretty straightforward except for the PLL.

The trick is to make everything stable to picoseconds. The entire system error budget is 100 ps, of which I can claim a small share.

An NCO doing Fc*125/1944 and clocked at Fc=155.52 MHz would put out 10 MHz, with small cycle-to-cycle errors in a pattern that repeats every 12.5 us. Easy to do in binary in an FPGA.

Jeroen Belleman

Apparently some snacks were allowed:

Sure.

Going back to "Ultra low noise claim of the 6948f" data sheet above, I now see that at ~2.5Ghz it is -100dBc at 100k offset, and -130dBc at 1MHz. A decent x9 (277Mhz->2.5Ghz) LC tank design should come it at around -145 dBc at those frequency offsets. So ultra low noise appears to be relative to the claimer :-)

Kevin Aylward

You will need to give me a heads up on what applications this delay change will matter. Temperature changes are typically sub Hz. Once equipment warms up, it could be minutes for a one degree change in temperature. The steady state frequency won't change, its n x input f. Considering that say, a 10MHz oscillator might hit -100 dBc at 10 Hz offset compared to its wonderful -160dBc flatband (100kHz +) , systems, in general have to be a lot more tolerant of close in phase noise.

Its a fact that many main stream high performance xtal oscillator vendors use LC tanks to up-convert the xtal frequency to achieve lower noise than is available from a PLL. You seem to be implying that there is some flaw with this approach for some applications. I would be interested to know the details.

Kevin Aylward

In John's application, it will make the 10 MHz BPF the dominant source of drift in the whole board, because it's outside the loop.

Cheers

Phil Hobbs

Inevitably. The marketing department again. Of course a nice YIG-tuned oscillator like the ones in the HP8568 can be >100 dB down at 100 Hz.

Cheers

Phil Hobbs

I never really understood yigs. How do you control the magnetic field to super-precise levels?

I've never designed one myself. Usually there are two coils, one coarse and slow, the other fine and fast. It's easy to make something quiet if you can make it very slow in the process.

Cheers

Phil Hobbs

Right. I need a 10 MHz bandpass filter with really small delay vs temperature behavior. Another annoyance, designing a filter and analyzing its sensitivities and compensating inductors with NTC caps, or something. Probably I'll measure ambient temp and let the uP tweak overall delay to nominally zero. That sort of thing will typically result in a 5:1, maybe even 10:1, TC reduction. I don't want to temperature cycle units in production, so the slope compensation would be determined on the first unit and applied to all the rest, if possible.

Inductors of the type we'd use here seem to have TCs in the (roughly)

On a sunny day (Mon, 15 Sep 2014 13:22:06 -0400) it happened Spehro Pefhany wrote in :

Nice, watched all 4 episodes.