To generate frequencies from approximately 0.5 mHz to 12 MHz with a DDS a minimum clock of >24, say 25 MHz, is required. To be able to go down to 0.5 mHz, a phase accumulator of at least 36 bits is required. This will give sub mHz resolution over the entire range. Nice for the low frequencies, but not of much use for MHz frequencies (in this application).

Is there any objection to using a smaller phase accumulator and a clock pre-scaler to generate the lower frequencies?

I see Analog Devices has DDS chips up to 48 bits, so 36 bits would not be a problem (except for cost maybe).

But al of the DDS chips I find from Analog seem only to implement a fixed sine table/function. Do DDS chips exist that allow downloading an arbitrary lookup table with 2^10 - 2^16 entries of 10 - 16 bit each?

If no such standard chips exist, I expect I need to implement the DDS in an FPGA. Using a smaller accumulator would probably save some space in the FPGA. Or am I just optoimizing prematurely?

There is a STRONG objection to shortening the phase word. It will cause pr oblems with close in spurs (which can't be filtered) and reduces your resol ution. See below.

Instead of a pre-scaler, use a post divider. A pre-scaler on the clock to the DDS requires the analog filter to be adjusted to suit.

If you are looking to generate a non-sine waveform, it is not needed, or us eful.

Do you work at Highland Technology?

I've posted about an appropriate solution more than once in s.e.d. Here i s a fair summary...

A DDS should be designed to generate a top frequency over a 2:1 range. This is easy stuff, with good accuracy and very low jitter if properly designed , use of a LONG phase word and a good filter after the DAC. It is importan t to NOT shorten the phase word as that introduces spurs close to the frequ ency being generated, which can not be filtered out. This is because the t runcation of the phase word creates discontinuities which show up as close in spurs. Keep the phase word long and round the sine output to suit a 16 bit DAC. This generates harmonics which are much easier to filter.

You don't need to use a single large table for the sine. sin(a+b) = sin (a)cos(b) + cos(a)sin(b), where a is the msbs of the phase word and b is th e lsbs. Use appropriately sized tables for sin(a), cos(b) and a single tab le for the product cos(a)sin(b). This is practical if (a) and (b) are each truncated a bit. Because sin(b) is always small, this term is always smal l and does not need to be calculated with full resolution on a and b. This product table also does not require the full word width. Three table look ups, one multiply and one add.

A programmable divider then divides the top frequency by 2**N by counting u p to a settable value.

The top frequency can clock a final FF buffer register of your favorite tec hnology to provide the actual pulse output with an appropriate jitter.

The settings of these two units can both be changed on a single clock cycle by writing to a buffer register and updating the actual operational regist ers simultaneously on a cue. The DDS will continue from the present phase, so will produce one top frequency clock pulse that is an intermediate perio d. The programmable divider will continue from the current count, either tr iggering right away, or continuing to count from the present value. Either way it will produce one output pulse that is within the range of the two se ttings, the prior setting and the new setting.

Does this make sense? Feel free to drop my name with your boss.

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Ah yes, changing the clock would require adjustment of the output filter. Not something you would want to do.

How would you post-divide the (arbitrary waveform) output? Or do you mean something else with the post-divide?

Could you explain this? How would I generate an arbitrary waveform without using a table?

No, I do not.

I don't read there, so missed that. But are you now talking about an appropriate solution for a specific Highland Technology problem, or a general solution?

Not really. I don't need just a sin(a+b) signal, I need to implement arbitrary (not realy arbitrary, but various rather complex) waveforms. I don't see how your solution will do this, unless I totally misunderstood it.

I can do that, but I doubt it it will ring a bell, even with your full name. I believe we live on different continents, so I don't think we have ever met.

Well, your frequency will be less accurate. To see this let me derive formula for DDS. Let t be DAC clock, T be period of desired signal and assume that we have N samples at uniformly distributed points. At n-th tick of DAC clock real time is nt. In the scale of desired signal this corresponds to nt/T. To get position within period we drop integer part of this, that is take frac(nt/T). Then we need to round to closest sample point. Actually instead of rounding we can multiply by N, add 0.5 as bias and take integer part. So, sample index is:

[N frac(nt/T) + 0.5]

where [ ] denotes integer part. Assuming that N is power of 2, say 2^m and all arthmetic is in fixed point binary frac above is equvalent to dropping high bits, leaving only m bits before binary point. Integer part means dropping bits after bianary points. So formula simplified to

[nNt/T + 0.5] = [n*a + b]

where a = Nt/T and b = 0.5 is time shift. Note that taking

phi_n = n*a + b

we have phi_{n+1} = (n+1)*a + b = a + phi_n so single addition is enough to adjust phase. What is effect of using smaller number of bits to represent phase phi_n? Well, b needs only

1 bit, so if Nt/T fits into k bits with k bigger than m + 1, then calculation using k bits gives exactly the same result as calculation using infinite precision. In other words, using k bits we get exact result but possibly for wrong frequency.

In general acceptable frequency error depends on application. But since good analog components are more expensive than digital ones, simple heuristic says that resuluting of phase accumulator should not degrade accuracy of oscilator. Assuming few ppm quartz oscilator as source of DAC clock, this means that we need about 20 significant bits in parameter a. OTOH, at moderate freqences we do not want to make big jumps, so parameter a should have m or more zero bits at start. With m = 10 we arrive at 30 bits. Add some margin for users that want slightly better results and we arrive at 36 bits. In fact, if you want 0.5 mHz without divisor on DAC clock you will have about 35 zero bits at start of paramter a, so 55 bits phase accumultor would be more appropriate. However, in in few hundreds Hertz range and below pre-divisor on DAC clock seem quite appropriate, so 36 bits + pre-divisor should be OK.

If you go for 25 MHz DAC clock your DDS should be doable using sufficiently fast processor. My rough guesstimate is that to produce single sample (addjust phase accumulator, extract bits and copy value) you need about 10 machine instructions, so 250 MIPS processor should be fast enough to generate samples. You probably need a DMA channel to transmit them to DAC. I am not aware of processor with fast enough DAC, but I think that there are processors capable of driving external DAC at that speed.

OTOH with 12 MHz signal and 25 MHz DAC clock you essentially are limited to sinusoidal signals, to have more variety you need more samples per period, so either lower signal frequency or higher DAC clock. So you may end up with much higher DAC freqency and censequenty be forced to use FPGA.

As I wrote earler, skimming bits on phase accumulator seems unwise, it is at most one instruction in critical loop in CPU realization and has _much_ smaller impact on FPGA (think about size of your tables, single counter is tiny compared to that).

problems with close in spurs (which can't be filtered) and reduces your re solution. See below.

to the DDS requires the analog filter to be adjusted to suit.

n

r useful.

It's not without a table, but not one huge table, 2^n length where n is the number of phase bits. I described the process below.

Ok, someone there was inquiring about the exact same thing and often has on e of his people enquire about such problems here when they potentially invo lve FPGAs. Sorry I mistook you for that.

is a fair summary...

The DDS is general. A single sine table is fine if you have the memory for it. But you can do very well with numerical methods and much smaller tabl es as well.

This is easy stuff, with good accuracy and very low jitter if properly desi gned, use of a LONG phase word and a good filter after the DAC. It is impor tant to NOT shorten the phase word as that introduces spurs close to the fr equency being generated, which can not be filtered out. This is because the truncation of the phase word creates discontinuities which show up as clos e in spurs. Keep the phase word long and round the sine output to suit a 16 bit DAC. This generates harmonics which are much easier to filter.

in(a)cos(b) + cos(a)sin(b), where a is the msbs of the phase word and b is the lsbs. Use appropriately sized tables for sin(a), cos(b) and a single ta ble for the product cos(a)sin(b). This is practical if (a) and (b) are each truncated a bit. Because sin(b) is always small, this term is always small and does not need to be calculated with full resolution on a and b. This p roduct table also does not require the full word width. Three table lookups , one multiply and one add.

ng up to a settable value.

technology to provide the actual pulse output with an appropriate jitter.

ycle by writing to a buffer register and updating the actual operational re gisters simultaneously on a cue. The DDS will continue from the present pha se, so will produce one top frequency clock pulse that is an intermediate p eriod. The programmable divider will continue from the current count, eithe r triggering right away, or continuing to count from the present value. Eit her way it will produce one output pulse that is within the range of the tw o settings, the prior setting and the new setting.

Ok, if you need an AWG, then you need a large memory. Your original post d idn't seem to mention that. It only talked about sine waves.

Sorry, I was mistaken thinking you worked at Highland Tech.

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In sine generation, it is often used in applications where spurs need to be minimized. A filter is good for a sine wave, but is limited on removing c lose in spurs. Truncation of the phase word (even just as an input to the sine generator) creates spurs close to the fundamental. It essentially cre ates phase discontinuities that manifest as close in spurs. These are virt ually unfilterable. If jitter or close in spurs are not important, then sh ortening the phase word has other obvious limitations that can be evaluated readily.

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se problems with close in spurs (which can't be filtered) and reduces your resolution. See below.

k to the DDS requires the analog filter to be adjusted to suit.

ot

an

or useful.

he number of phase bits. I described the process below.

Opps, to correct myself... 2^(n-2) length table if you take advantage of t he folding properties of the sine function.

S

ce

one of his people enquire about such problems here when they potentially in volve FPGAs. Sorry I mistook you for that.

re is a fair summary...

r it. But you can do very well with numerical methods and much smaller tabl es as well.

. This is easy stuff, with good accuracy and very low jitter if properly de signed, use of a LONG phase word and a good filter after the DAC. It is imp ortant to NOT shorten the phase word as that introduces spurs close to the frequency being generated, which can not be filtered out. This is because t he truncation of the phase word creates discontinuities which show up as cl ose in spurs. Keep the phase word long and round the sine output to suit a

16 bit DAC. This generates harmonics which are much easier to filter.

sin(a)cos(b) + cos(a)sin(b), where a is the msbs of the phase word and b i s the lsbs. Use appropriately sized tables for sin(a), cos(b) and a single table for the product cos(a)sin(b). This is practical if (a) and (b) are ea ch truncated a bit. Because sin(b) is always small, this term is always sma ll and does not need to be calculated with full resolution on a and b. This product table also does not require the full word width. Three table looku ps, one multiply and one add.

ting up to a settable value.

te technology to provide the actual pulse output with an appropriate jitter .

cycle by writing to a buffer register and updating the actual operational registers simultaneously on a cue. The DDS will continue from the present p hase, so will produce one top frequency clock pulse that is an intermediate period. The programmable divider will continue from the current count, eit her triggering right away, or continuing to count from the present value. E ither way it will produce one output pulse that is within the range of the two settings, the prior setting and the new setting.

I
d

didn't seem to mention that. It only talked about sine waves.

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That is assuming the processor has not much else to do and that only a single DDS channel is required. Both will not be true in the possible application, I'm affraid. The additional DDS channels can be a bit slower, so it may still be doable.

Yes, this is understood. Read the 10 MHz as bandwidth, not as the max frequency at which a complex waveform should be generated. So the waveform will degrade to a sine when sped up to 10 MHz.

FPGA have memory blocks to hold such tables. A simple ripple counter will indeed take a tiny amount of logic, a synchronous counter will take more, certainly at 55 bits. But I think you need an adder if you want variable accumulator steps and not only +1. Keeping the adder small enough to fit in something like a 48-bit DSP slice will probably save space.

The above is probably quite Xilinx specific, as that is the last FPGA I have experience with. And even that was a while ago.

But again, I may be worrying too much about space already. When it comes to it, I should first implement the 'best' solution. And then probably find that this uses less than 10% of my FPGA. :-)

--
Stef
Don't shout for help at night. You might wake your neighbors.

I suspected something like this was the case, no problem. :-)

Yes DDS is general. But your method seemed to be aimed specifically at a certain problem. But if I understand you correctly, the method you describe is a general solution to generate sine waves without large tables?

Re-reading my original post, I see that was a bit hidden in the text and may not have been clear to a reader not familiar with the application. Sorry about that.

I thought you might have. ;-)

--
Stef
Hey, I had to let awk be better at *something*... :-)

You keep calling it a DDS, which apparently is correct in that it can be us ed generically. But conventionally this refers to generating a sine wave. The term, AWG (Arbitrary Waveform Generator) is more commonly used for wha t you are doing.

Ripple or synchronous would be the same, 1 FF and 1 LUT per bit. That's as suming an FPGA that supports addition in the LUT/FF cell, which most do. E ven if your increment is +1, that uses the same logic because it's still 1 LUT. Of course, if you have other inputs, such as an enable or add/sub

Yes, unless you have *a lot* going on in the FPGA, you won't need to worry about a 55 bit counter, running at 50 MHz. It won't be significant in your greater design.

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Rick C.
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the number of phase bits. I described the process below.

DS

ace

s one of his people enquire about such problems here when they potentially involve FPGAs. Sorry I mistook you for that.

ere is a fair summary...

for it. But you can do very well with numerical methods and much smaller ta bles as well.

Yes, only sine waves. If you need an AGW, you need a large table, unless t he waveform can be described mathematically in ways that can be synthesized in logic. Like combinations of sawtooth, triangle, sine, pulses, etc. Th at can be done with counters and added together.

t didn't seem to mention that. It only talked about sine waves.

You can combine the table with logic to produce a "sparse" waveform. Such as a burst of arbitrary data, followed by no signal or some base signal tha t can be easily synthesized, followed by another burst of arbitrary data. There's no limit to the combinations you might think of to suit a given pro blem.

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Rick C.
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On 2022-08-18 snipped-for-privacy@gmail.com wrote in comp.arch.fpga:

To me, the core of the DDS is the clock/phase accumulator/control word. The phase output of this can be fed to any phase to amplitude conversion you like. Complete DDS chips often include sine (table), sawtooth (direct phase to DAC) and pulse (MSB of phase).

Although not an authoritive source, wikipedia agrees with this interpretation.

formatting link

AWG, to me, just means you can generate any waveform. But not how you set the frequency of this waveform. It can be fixed or just use divide by 2 stages on the clock, or wathever.

But this is all just personal interpretations, I think we both understand what the other means right now. Maybe we should call it an DDS AWG generator to cover everything. ;-)

--
Stef
The party adjourned to a hot tub, yes. Fully clothed, I might add.

Sorry, I didn't mean to make a big deal of the nomenclature. So what are you trying to do that isn't obvious, given a phase accumulator and a lookup table?

The frequency is normally set by the increment on the phase accumulator. But maybe that doesn't work so well for an AWG? What sort of waveforms are you interested in generating?

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Rick C.
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I suppose to control the sample rate of the AGW, you could use a DDS with a clock output. The DDS would give a wide range of frequency with high resolution. What range of sample rate are you interested in?

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Rick C.
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I think it is obvious. Phase accumulator points to LUT, but LUT isn't a sine table but sommething else.

This is the DDS part (as I interpret it) and this is what I intend to do. I see no reason why this would not work for AWG. Except when you get to higher frequencies, you start losing your waveform, until it degrades to a sine at FS/2 (providing the output filter is correct).

For now, I need to accomodate 'anything you can draw'. So a full phase to amplitude LUT is required. Length and width TBD.

--
Stef
Don't read any sky-writing for the next two weeks.

Normally for a Arbitrary Waveform, the phase increment is limited to no more that one LUT entry per clock cycle, and if there aren't an integral number of increments per phase increment of one LUT entry, you want there to be a moderate number to avoid "distortion" of the waveform.

And you need to decide how the "Arbitrary" waveform is shaped between points, normally either step held or lineally interpreted.

Yes, it is obvious. That's why I'm asking what you are looking for from this discussion.

I'm not following what you are saying about your filter. It only needs to filter artifacts above the Nyquist rate of fs/2. It would not need to distort your waveform.

Yes, if you want "anything you can draw", you need the LUT. But many waveforms can be constructed from simple shapes which can be generated digitally. The LUT won't be able to use the folding techniques that work for sine waves.

I don't know what your requirements are, but you can buy low cost AWG board level products and small box level products.

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Rick C.
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1) Are there objections to using a prescaler and a shorter phase accumulator for generating frequencies over a wide range?

This has been discussed. Conclusions is that you should keep the accumulator as long as possible for best performance.

2) Are the complete DDS chips available that have a downloadable LUT, instead of the standard sine table?

If such chips are available, I may not have to develop a custom (FPGA/CPU/DSP) solution. This question has not been answered and I have found non myself sofar.

...

At this time there are only general requirements (AWG, 12MHz BW, ...). If the project continues, this will be detailed further.

Do you have an example of such a board level product? If it can do what will be required, it is certainly an option.

--
Stef
If everything seems to be going well, you have obviously overlooked something.

If any of that is from my comments, I retract them. I was thinking of a ty pical DDS generating a sine wave.

You only need the clock rate to suit the waveform you are generating, such as Nyquist considerations. Your memory is finite, so you have a fundamenta l trade off between clock rate and duration of the AWG pattern. I don't kn ow your real requirements, so I can't advise you about how to optimize this . It will depend on your particular problem.

Yeah, I've never used DDS chips, so I couldn't say. As I've mentioned, th ere are many AWG products at other levels of integration, modules and board s. eBay abounds with them.

oard level products and small box level products.

Try punching AWG into eBay or one of the other sites.

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Rick C.
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Most of those comments (and of Waldek) will also apply to AWG in some way, so no need to retract. Also the output filter argument is one against switching sample frequency. Ofcourse I can keep the pre-scaler option in mind, but I don't think it should be the initial approach. Only an optimization when really necessary (speed, size, etc).

Searching on AWG alone will find you a lot of wire. ;-) With "arbitrary waveform generator", I get a lot of complete bench top generators. And a number of (usually the same) cheap bare board units like this one:

formatting link

This one is 8-bit 256 sample 100 kSPS. Not enough on every parameter and it seems most of these modules have similar specs.

But this is the kind of board level product you meant? I hoped for someting that can be placed on a board. Looks like I need to implement something myself if this project continues.

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