ðpÉ×ÅÔÓÔ×ÕÀ, Vladimir!
VB> ÷ÏÔ ÈÏÞÕ ÐÏÐÒÏÂÏ×ÁÔØ ÓÄÅÌÁÔØ ÄÌÑ ÓÁÍÏÏÂÒÁÚÏ×ÁÎÉÑ ÐÒÏÅËÔ ÎÁ VHDL, É VB> ÓÔÏÌËÎÕÌÓÑ Ó ÐÒÏÂÌÅÍÏÊ ËÏÔÏÒÕÀ ÎÅ ÐÏÎÉÍÁÀ. ðÉÛÕ ÎÁ VHDL ÄÌÑ XC9536, É VB> ×ÏÔ × ÏÄÎÏÍ ÉÚ ÍÏÄÕÌÅÊ ÎÅ ÐÒÏÉÓÈÏÄÉÔ ÐÒÁ×ÉÌØÎÁÑ ÉÎÉÃÉÁÌÉÚÁÃÉÑ VB> ÍÁËÒÏÑÞÅÅË. úÁÂÕÄØ ÐÒÏ ÄÅÆÏÌÔÎÙÅ ÚÎÁÞÅÎÉÑ. éÈ ÍÏÖÎÏ ÉÓÐÏÌØÚÏ×ÁÔØ ÔÏÌØËÏ ÄÌÑ ÓÉÍÕÌÑÃÉÉ. ðÒÁ×ÉÌØÎÁÑ ÐÒÁËÔÉËÁ - ÉÍÅÔØ ÏÔÄÅÌØÎÙÊ ×ÈÏÄ ÓÂÒÏÓÁ, ÐÏ ËÏÔÏÒÏÍÕ ÕÓÔÁÎÁ×ÌÉ×ÁÀÔÓÑ ÎÕÖÎÙÅ ÔÅÂÅ ÕÍÏÌÞÁÔÅÌØÎÙÅ ÚÎÁÞÅÎÉÑ. áÓÉÎÈÒÏÎÎÙÊ ÉÌÉ ÓÉÎÈÒÏÎÎÙÊ ÓÂÒÏÓ - ÒÅÛÁÔØ ÐÏ ÍÅÓÔÕ, ÎÏ ÓÂÒÏÓ ÂÙÔØ ÄÏÌÖÅÎ. VB> ðÒÉ ÔÅÓÔÉÒÏ×ÁÎÉÉ ËÁÖÄÏÇÏ ÍÏÄÕÌÑ ÄÉÁÇÒÁÍÍÙ ÎÁÞÉÎÁÀÔÓÑ Ó VB> ÐÒÁ×ÉÌØÎÏÇÏ ÐÏÌÏÖÅÎÉÑ, Á ×ÏÔ Fitter report ÓÏÏÂÝÁÅÔ, ÞÔÏ ÑÞÅÊËÉ Hour VB> ÕÓÔÁÎÏ×ÌÅÎÙ ÔÁË ËÁË Ñ ÎÁÐÉÓÁÌ, Á Minutes - ×ÓÅ ÂÕÄÕÔ × SET-ÓÏÓÔÏÑÎÉÉ. VB> ÷ ÖÅÌÅÚÏ Ñ ÅÝÅ ÎÅ ÚÁÌÉ×ÁÌ. ÷ӣ ÐÒÁ×ÉÌØÎÏ, ÔÁË É ÄÏÌÖÎÏ ÂÙÔØ. äÏÂÁ×Ø Ë ËÁÖÄÏÍÕ ÓޣÔÞÉËÕ ÓÂÒÏÓ ÷ ÉÄÅÁÌÅ - ÐÒÉÍÅÒÎÏ ÔÁË:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.all; use IEEE.STD_LOGIC_ARITH.all;
entity count is Generic( Width: integer := 8; -- ÒÁÚÒÑÄÎÏÓÔØ ÓޣÔÞÉËÁ Preload_RST: integer := 10; -- ÞÉÓÌÏ, ÚÁÇÒÕÖÁÅÍÏÅ ÐÒÉ ÁÓÉÎÈÒÏÎÎÏÍ ÓÂÒÏÓÅ Preload_SRST: integer := 13 -- ÞÉÓÌÏ, ÚÁÇÒÕÖÁÅÍÏÅ ÐÒÉ ÓÉÎÈÒÏÎÎÏÍ ÓÂÒÏÓÅ ); Port( count_enable : in STD_LOGIC; -- ÅÓÌÉ 1 - ÉÚÍÅÎÑÅÍ ÓޣÔÞÉË ÓÏÏÔ×ÅÔÓÔ×ÅÎÎÏ inc_dec inc_dec : in STD_LOGIC; -- ÅÓÌÉ 1 - Õ×ÅÌÉÞÉ×ÁÅÍ ÓޣÔÞÉË, 0 - ÕÍÅÎØÛÁÅÍ load : in STD_LOGIC; -- ÅÓÌÉ 1 - ÚÁÇÒÕÖÁÅÍ ÓޣÔÞÉË ÉÚ count_load count : out STD_LOGIC_VECTOR(Width-1 downto 0); -- ×ÙÈÏÄ ÓޣÔÞÉËÁ count_load : in STD_LOGIC_VECTOR(Width-1 downto 0); -- ×ÈÏÄ ÚÁÇÒÕÚËÉ ÓޣÔÞÉËÁ CLK : in STD_LOGIC; -- ÒÁÂÏÔÁÅÍ ÐÏ ÆÒÏÎÔÕ CLK SRST : in STD_LOGIC; -- ÓÉÎÈÒÏÎÎÙÊ ÓÂÒÏÓ ÐÏ 1 RST : in STD_LOGIC -- ÁÓÉÎÈÒÏÎÎÙÊ ÓÂÒÏÓ ÐÏ 1 ); end count; architecture behavioral of count is signal count_internal : STD_LOGIC_VECTOR (Width-1 downto 0); begin process (CLK,RST) begin if (RST='1') then count_internal <= CONV_STD_LOGIC_VECTOR(Preload_RST,Width); elsif (rising_edge(CLK)) then if (SRST='1') then count_internal <= CONV_STD_LOGIC_VECTOR(Preload_SRST,Width); elsif (load='1') then count_internal <= count_load; elsif (count_enable='1') then if (inc_dec='1') then count_internal <= count_internal + '1'; else count_internal <= count_internal - '1'; end if; end if; end if; end process; count <= count_internal; -- Á ÜÔÏ ÎÕÖÎÏ, ÞÔÏÂÙ ÉÚÂÅÖÁÔØ ÏÛÉÂËÉ "×ÙÈÏÄÎÏÊ ÓÉÇÎÁÌ × ÜÔÏÍ ÇңÂÁÎÏÍ
-- VHDL ÐÒÏÞÉÔÁÔØ ÎÅÌØÚÑ, ÂÌÉÎ !"
-- PS: ÉÚ-ÚÁ ËÏÔÏÒÏÊ ÔÙ ÎÁ×ÅÒÎÑËÁ É ÓÄÅÌÁÌ ×ÙÈÏÄÙ ÓޣÔÞÉËÏ× ËÁË inout :)
-- PPS: ÐÏÐÒÏÂÕÊ Verilog - ÐÒÉÇÏÄÉÔÓÑ, ÔÁËÉÈ ÍÅÌÏÞÎÙÈ ÐÒÅÔÅÎÚÉÊ ÔÁÍ ÎÅÔ...
-- PPPS: ....ÎÏ É VHDL ÎÅ ÚÁÂÙ×ÁÊ ! end behavioral; ôÅ ÖÅ ÑÊÃÁ, ÔÏÌØËÏ ÎÁ Verilog: `timescale 1ns / 1ps module count( count_enable, inc_dec, load, count, count_load, CLK, SRST, RST ); // ÐÁÒÁÍÅÔÒÙ parameter Width = 8; // ÒÁÚÒÑÄÎÏÓÔØ ÓޣÔÞÉËÁ parameter Preload_RST = 10; // ÞÉÓÌÏ, ÚÁÇÒÕÖÁÅÍÏÅ ÐÒÉ ÁÓÉÎÈÒÏÎÎÏÍ ÓÂÒÏÓÅ parameter Preload_SRST = 13; // ÞÉÓÌÏ, ÚÁÇÒÕÖÁÅÍÏÅ ÐÒÉ ÓÉÎÈÒÏÎÎÏÍ ÓÂÒÏÓÅ // ÐÏÒÔÙ input count_enable; // ÅÓÌÉ 1 - ÉÚÍÅÎÑÅÍ ÓޣÔÞÉË ÓÏÏÔ×ÅÔÓÔ×ÅÎÎÏ inc_dec input inc_dec; // ÅÓÌÉ 1 - Õ×ÅÌÉÞÉ×ÁÅÍ ÓޣÔÞÉË, 0 - ÕÍÅÎØÛÁÅÍ input load; // ÅÓÌÉ 1 - ÚÁÇÒÕÖÁÅÍ ÓޣÔÞÉË ÉÚ count_load output [Width-1:0] count; // ×ÙÈÏÄ ÓޣÔÞÉËÁ input [Width-1:0] count_load; // ×ÈÏÄ ÚÁÇÒÕÚËÉ ÓޣÔÞÉËÁ input CLK; // ÒÁÂÏÔÁÅÍ ÐÏ ÆÒÏÎÔÕ CLK input SRST; // ÓÉÎÈÒÏÎÎÙÊ ÓÂÒÏÓ ÐÏ 1 input RST; // ÁÓÉÎÈÒÏÎÎÙÊ ÓÂÒÏÓ ÐÏ 1 reg [Width-1:0] count; // ÇÏ×ÏÒÉÍ, ÞÔÏ ÓޣÔÞÉË Õ ÎÁÓ - ÒÅÇÉÓÔÒ // ÓÏÂÓÔ×ÅÎÎÏ ËÏÄ always@(posedge CLK or posedge RST) if (RST) count = Preload_RST; else if (SRST) count = Preload_SRST; else if (load) count = count_load; else if (count_enable) if (inc_dec) count = count + 1'b1; else count = count - 1'b1; endmodule // count VB> minutes : inout STD_LOGIC_VECTOR (9 downto 0) := "0000000001"; ä×ÕÎÁÐÒÁ×ÌÅÎÎÙÊ ÐÏÒÔ ÓÄÅÌÁÌ ÉÚ-ÚÁ ÐÒÏËÏÍÍÅÎÔÉÒÏ×ÁÎÎÏÊ ×ÙÛÅ ÏÛÉÂËÉ ? ôÏÇÄÁ ÒÅÛÅÎÉÅ ÇÏÔÏ×Ï :) ÷ ÜÔÉÈ CPLD ×ÎÕÔÒÉ Ä×ÕÎÁÐÒÁ×ÌÅÎÎÙÈ ÛÉÎ ÎÅÔ, ÔÁË ÞÔÏ Ô×ÏÊ inout ÂÕÄÅÔ ÎÅÑ×ÎÏ ÐÒÅÏÂÒÁÚÏ×ÁÎ × ÔÅ ÖÅ ÓÁÍÙÅ Ä×Å ÛÉÎÙ, ÐÒÉޣÍ ÈÒÅÎ ÚÎÁÅÔ ËÁË. ÷ÏÏÂÝÅ Ä×ÕÎÁÐÒÁ×ÌÅÎÎÙÅ ÛÉÎÙ ÐÒÉÍÅÎÑÀÔÓÑ Ó ÏÇÌÑÄËÏÊ, × ÏÓÎÏ×ÎÏÍ ÅÓÌÉ ÎÁÄÏ Ó ×ÎÅÛÎÉÍ ÍÉÒÏÍ Ó×ÑÚÁÔØÓÑ. ÷ÎÕÔÒÉ - ÒÅÄËÏ, É ÔÏÌØËÏ ÅÓÌÉ ÅÓÔØ ×ÎÕÔÒÅÎÎÉÅ Ä×ÕÎÁÐÒÁ×ÌÅÎÎÙÅ ÛÉÎÙ × ËÒÉÓÔÁÌÌÅ (Virtex Ë ÐÒÉÍÅÒÕ).
Michael Tulupov ...