How process statement works in vhdl

Question

Hello, I a newer to vhdl. I am trying to change my algorithm form matlab to vhdl. I met RAMs conflict when I did it.

*********************************************************** library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

library unisim; use unisim.vcomponents.all;

entity dcdtest3 is generic (Nit: integer:=20000; H: integer :=1; Mb: integer :=6);

port ( clk: in std_logic; en: in std_logic; b: in std_logic_vector(15 downto 0); r: in std_logic_vector(15 downto 0); dout1: out std_logic_vector(15 downto 0); dout2: out std_logic_vector(15 downto 0)); end dcdtest3;

architecture behaviour of dcdtest3 is function maxfunction( arg1, arg2, arg3: std_logic_vector (15 downto

0)) return std_logic_vector ; type ram_type1 is array (0 to 3) of std_logic_vector(15 downto 0); signal ramb : ram_type1 :=(others =>(others=>'0')); signal ramh : ram_type1 :=(others =>(others=>'0')); signal ramrtmp: ram_type1 :=(others =>(others=>'0')); type ram_type2 is array (0 to 15) of std_logic_vector (15 downto 0); signal ramr : ram_type2:=(others =>(others=>'0')); signal douts1: std_logic_vector(15 downto 0) :=(others=>'0'); signal douts2: std_logic_vector(15 downto 0) :=(others=>'0'); signal trigger: std_logic :='0';

begin dout1

backhus · Accepted Answer

Hi,you made a common mistake. Multiple assignment.In both processes writeramb and Algorithm you assign values to signalramb.Your simulator detects this and resolves the conflicting values to 'X'.Your synthesis tool will generate an error.Think of processes as integrated circuits. (Their enclosure is Begin and end) There you would never tie normal (compared to tristate) outputs together because it may lead to shortening the supply and destruction of the ICs.Furthermore, If you want to enable some clocked process better write:if rising_edge(clk) then   if trigger = '1' then      --do something   end if;end if;If you want to intialize your ram, you have to do it in another way.For example in a single process.have a nice synthesis   EilertZHI schrieb:....***************************************************************************************

ZHI · Answer

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How process statement works in vhdl

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