hi
ich have a problem with a project in ise and modelsim. i used the core generator to create a single port block memory and instantiated it in my design. now i want to do a behavioral simulation to verify my design. i followed the instructions from the core generator help file. ( i used the *.vho file to instantiate the block memory in my design and downloaded the latest libraries from xilinx for model sim).
but whatever i do to the ports of the memory they always stay 'x'. shouldn't at least the input port be '0' or '1' if i apply that signal?
here is the way i instantiated it:
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all;
use work.spi_package.all;
entity spi_memory is PORT ( CLK : in STD_LOGIC; Data_in : inout STD_LOGIC_VECTOR (31 downto 0); Data_out : inout STD_LOGIC_VECTOR (31 downto 0); Address : in STD_LOGIC_VECTOR (9 downto 0); WR : in STD_LOGIC; RD : in STD_LOGIC); end spi_memory;
architecture Behavioral of spi_memory is
component spi_mem port ( clka : IN std_logic; dina : IN std_logic_VECTOR(31 downto 0); addra : IN std_logic_VECTOR(9 downto 0); wea : IN std_logic_VECTOR(0 downto 0); douta : OUT std_logic_VECTOR(31 downto 0)); end component;
-- Synplicity black box declaration
-- attribute syn_black_box : boolean;
-- attribute syn_black_box of spi_mem: component is true;
signal s_write_strobe : std_logic;
begin
I_spi_mem: spi_mem port map ( clka => CLK, dina => Data_in, addra => Address, wea => vectorize(s_write_strobe), douta => Data_out);
GENERATE_WRITE_STROBE: process(WR, RD, Address) begin
s_write_strobe = "0000001010" then
s_write_strobe