Hi
I have a simple VHDL counter modul that I wanna debug with Chipscope 7.1 on a Virtex II board:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;
entity top is port ( clk : in std_logic := ?0?; cnt : out std_logic_vector(3 downto 0) ); end top;
architecture behave of top is signal counter : std_logic_vector(31 downto 0) := (others => ?0?); begin process(clk) begin if ( clk?event and clk = ?1? ) then counter
Do you have a clock, and what is the frequency? Have you checked that the outputs are running? That is a big counter, so even at 50MHz, cnt[0] should be toggling once every 5 seconds or so (if I didn't mess up my quick calculations). Even if you don't have an oscilloscope, you can see that with a plain voltmeter.
Hi Paul,
That's the problem. The clock is slow or stopped. HTH., Syms.
p.s. Unrelated, but you should use numeric_std.
Hm yeah, maybe I have forgotten the clk then completly? I thought through the net connection to clk_BUFG of clk the clock connecntion is established?
For simulation I used this code:
process begin CLK
That's probably your problem right there. I don't use the ISE GUI at all - I run everything from the command line, so I can't help with that. I manually instantiate the ICON and ILA modules within my design and copy the *.edn files into my build directory.
Your ILA needs a clock signal to sample the state of the trigger ports. Are you using an eval board? Doesn't it have an oscillator on it?
Alright, I use the core inserter for this task but at the end of day both should work properly. When I select the net for the clock I can use either clk_BYFGP with Base Type BUFGP or clk with base type port. If I try using BUFGP nothing happens as stated in my first post. If I use clk and run synthesis I get the following error message:
NgdBuild:924 - input pad net 'clk' is driving non-buffer primitives
Although a very basic question, but where is the input port for my clk coming from. DO I need to write my own oszilator? Or does the FPGA automatically detect the clk signal and know what to do?
Cheers,
The FPGA does not automatically detect the clock, and you do not really want to try to generate an oscillator internal to the FPGA in most cases.
What board are you using? It should have one or more oscillators on it that go to the FPGA. The documentation should tell you what pin each clock signal goes to. You use the UCF file to associate the pins with the signal names in top level of your FPGA design. Choose one of the available clocks, buffer it with a BUFG, and use the output of the BUFG as the clock signal to your logic.
Regards,
John McCaskill
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