Xilinx ModelSim VHDL Running Two Models

I assume you wish to simulate this?

This is Test Bench 101. You write a test bench and instantiate the DUT (your FPGA) and the SRAM model and any other models needed.

I assume you don't code your FPGAs in one huge source file with one huge entity, right?

You don't need to model trace delay if you're doing a functional simulation.

Hi Andy,

Thanks for spending the time.

Yes, with ModelSim from the Xilinx webpack.

Yes, I'm sure it seems rather obvious to you. However, it may not be to everyone. And there are very few text book examples of this.

It seems by what you are saying that the test bench would need to drive the inputs to the SRAM, unless there is some mechanism by which models can be tied together from the test bench. What is that?

I had thought that I would need a higher model, call it Board, that would instantiate both the FPGA, which I call top3, and the memory model. Board then would have something specifying the physical wires, like a signal for each of the traces, and an assignment statement (right term?) , like this:

signal board_srama : std_logic_vector(20 downto 0);

begin

board_srama

Brad I think you need a tutorial on testbenches... The usual way is to create a design (let's call it 'design') that will be synthesized. Then you create some sort of wrapper, the testbench, usually called design_tb in which you instantiate your design and all its environment (CPU, memory, DAC, ADC... ). This is where you will also generate the clock and reset signals. Don't worry about bidirectionnal signals at the testbench level. Treat all signals the same.

Nicolas

Quick add to my previous post: a VHDL tutorial is available here

Nicolas

Well, maybe you can show me an example, because I simply don't get it. You say you instantiate the CPU, memory, etc, but how does the simulator know what is connected to what?

Perhaps you can snip out one of your test-benches designs with bidirectional signals for me and the group?

That's a nice primer on VHDL but I don't see an example of a board design testbench. Would you care to point out the chapter?

Here's a rough skeleton. Assume your FPGA's top-level entity is called mychip, and the SRAM entity is called sram.

library ieee; use ieee.std_logic_1164;

entity mychip_tb is generic ( CLKPER : time := 10 ns; RESETTIME : time = 123 ns); end entity mychip_tb;

architecture testbench of mychip_tb is

-- globals: signal SysClk : std_logic; signal Reset_l : std_logic;

-- SRAM interface: signal RamAddr : std_logic_vector(18 downto 0); signal RamData : std_logic_vector(15 downto 0); signal RamCs_l : std_logic; signal RamWe_l : std_logic; signal RamOe_l : std_logic;

begin -- architecture testbench

u_dut : entity work.mychip port map ( SysClk => SysClk, -- global clock Reset_l => Reset_l, -- global reset RamAddr => RamAddr, -- SRAM address bus RamData => RamData, -- SRAM data bus RamCs_l => RamCs_l, -- SRAM chip select RamWe_l => RamWe_l, -- SRAM write enable RamOe_l => RamOe_l); -- SRAM read enable

u_sram : entity work.sram port map ( addr => RamAddr, -- SRAM address bus dq => RamData, -- SRAM data bus cs_l => RamCs_l, -- SRAM chip select we_l => RamWe_l, -- SRAM write enable oe_l => RamOe_l); -- SRAM output enable

ClkGen : process is SysClk

Hey Andy,

Thanks for the help.

I wrote the testbench below based on what you are saying.

However, I can't figure out how to get the memory model library to load. Once I have that figured out, I'll let you know.

Brad

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity toptb is end toptb;

architecture Behavioral of toptb is

component top3 port( x2clk : in std_logic ; reset_pin_in : in std_logic ; vga_hsync_out : out std_logic; vga_vsync_out : out std_logic; vga_rgb_red_out : out std_logic_vector(9 downto 0); vga_rgb_green_out : out std_logic_vector(9 downto 0); vga_rgb_blue_out : out std_logic_vector(9 downto 0); vga_clk_out : out std_logic; vga_synct_out : out std_logic; vga_sync_out : out std_logic; vga_blank_out : out std_logic; -- to SRAM sramclk : out std_logic; -- clock srama : out std_logic_vector(20 downto 0); -- address sramdqa : inout std_logic_vector(9 downto 1); -- data a sramdqb : inout std_logic_vector(9 downto 1); -- data b srame1 : out std_logic; -- chip enable 1 sramba : out std_logic; -- a data write enable srambb : out std_logic; -- b data write enable sramw : out std_logic; -- write enable -- from Xilinx U2 u2clk : in std_logic ; cam_line_in : in std_logic; -- via board VGADAT9 cam_data_in : in std_logic_vector(8 downto 0); -- TPA Switch tup_in : in std_logic; -- P198 tdown_in : in std_logic; -- P197 tleft_in : in std_logic; -- P194 tright_in : in std_logic; -- P196 tcenter_in : in std_logic; -- P199 -- Test led_out : out std_logic; test_out : out std_logic ); end component;

component G8320Z18T GENERIC ( CONSTANT ramtype : integer := 1; -- NBT=1 Burst=0 CONSTANT ramversion : integer := 1; -- 4->+1 RAM CONSTANT density : integer := 32; CONSTANT byteparl : integer := 4; CONSTANT A_size : integer := 21; CONSTANT DQ_size : integer := 9; CONSTANT bank_size : integer := 1024 * 2048;-- *32M /4 bytes in parallel CONSTANT tKQpipe : real := 3.4e+00 ;--166MHZ CONSTANT tKQflow : real := 8.0e+00) ;--166MHZ PORT ( SIGNAL A832 : IN std_logic_vector(A_size - 1 DOWNTO 0);-- address SIGNAL DQa : INOUT std_logic_vector(DQ_size DOWNTO 1) BUS;-- byte A data SIGNAL DQb : INOUT std_logic_vector(DQ_size DOWNTO 1) BUS;-- byte B data SIGNAL nBa : IN std_logic;-- bank A write enable SIGNAL nBb : IN std_logic;-- bank B write enable SIGNAL CK : IN std_logic;-- clock SIGNAL nCKE : IN std_logic;-- clock SIGNAL nW : IN std_logic;-- byte write enable SIGNAL nE1 : IN std_logic;-- chip enable 1 SIGNAL E2 : IN std_logic;-- chip enable 1 SIGNAL nE3 : IN std_logic;-- chip enable 1 SIGNAL nG : IN std_logic;-- output enable SIGNAL pADV : IN std_logic;-- Advance not / load SIGNAL ZZ : IN std_logic;-- power down SIGNAL nFT : IN std_logic;-- Pipeline / Flow through SIGNAL nLBO : IN std_logic);-- Linear Burst Order not end component;

signal sramclk : std_logic; -- clock signal srama : std_logic_vector(20 downto 0); -- address signal sramdqa : std_logic_vector(9 downto 1); -- data a signal sramdqb : std_logic_vector(9 downto 1); -- data b signal srame1 : std_logic; -- chip enable 1 signal sramba : std_logic; -- a data write enable signal srambb : std_logic; -- b data write enable signal sramw : std_logic; -- write enable

begin

u3_spartan3 : top3 port map( x2clk => x2clk, reset_pin_in => reset_pin_in, vga_hsync_out => vga_hsync_out, vga_vsync_out => vga_vsync_out, vga_rgb_red_out => vga_rgb_red_out, vga_rgb_green_out => vga_rgb_green_out, vga_rgb_blue_out => vga_rgb_blue_out, vga_clk_out => vga_clk_out, vga_synct_out => vga_synct_out, vga_sync_out => vga_sync_out, vga_blank_out => vga_blank_out, sramclk => sramclk, srama => srama, sramdqa => sramdqa, sramdqb => sramdqb, srame1 => srame1, sramba => sramba, srambb => srambb, sramw => sramw, u2clk => u2clk, cam_line_in => cam_line_in, cam_data_in => cam_data_in, tup_in => tup_in, tdown_in => tdown_in, tleft_in => tleft_in, tright_in => tright_in, tcenter_in => tcenter_in, led_out => led_out, test_out => test_out );

u21sram : G8320Z18T port map( A832 => srama, -- address DQa => sramdqa, -- byte A data DQb => sramdqb, -- byte B data nBa => sramba, -- bank A write enable nBb => srambb, -- bank B write enable CK => sramclk, -- clock nCKE => '0', -- clock enable nW => sramw, -- byte write enable nE1 => srame1, -- chip enable 1 E2 => '1', -- chip enable 1 nE3 => '0', -- chip enable 1 nG => '0', -- output enable pADV => '0', -- Advance not / load ZZ => '0', -- power down nFT => '1', -- Pipeline / Flow through nLBO => '0'); -- Linear Burst Order not

u2clk_proc : process is u2clk