Hello,
I'm working on a project targeting a Lattice Mach4 CPLD using VHDL. In the past I have never used the inout VHDL type, but with this design I am forced to. When I use Synplicity to synthesize though I get fanout errors for every bit in my inout signal:
Warning: network `cp20_main', node "PD_15_.BLIF" does not fanout ...
What exactly does this warning mean? I am hoping to use a single data bus for both input and output, tri-stating the output when it isn't used. Here is my latch that I'm using to output:
entity latch8 is port( clk:in std_logic; rst:in std_logic; data_in:in std_logic_vector(7 downto 0); latch_enable:in std_logic; output_enable:in std_logic; data_out:out std_logic_vector(7 downto 0)); -- this drives an inout in my top level end latch8;
architecture bhv of latch8 is signal data_latched: std_logic_vector(7 downto 0); begin process(clk,rst) begin if(rst='1') then data_latched