Hello For some reasons I have an IP with bidirectionnal IOs that is instantiated inside a higher level wrapper and that I can't modify. The proble is that the wrapper inserts some logic between an IO bus of the IP and the actual chip IOs. It seems that QuartusII (4.2) produces garbage from my VHDL. How can I do?
The problem is that int_bus is x"FF" when en = '1', instead of int_bus_in.
Sample code :
entity wrapper is port ( io_bus_1 : inout std_logic_vector(31 downto 0); io_bus_2 : inout std_logic_vector(31 downto 0); ... ); end entity wrapper;
architecture str of wrapper is signal en : std_logic; signal int_bus_in : std_logic_vector(7 downto 0); signal int_bus_out : std_logic_vector(7 downto 0); signal int_bus : std_logic_vector(7 downto 0);
component ip is port( io_bus_1 : inout std_logic_vector(7 downto 0); io_bus_2 : inout std_logic_vector(7 downto 0); ctrl : out std_logic; ... ); end component ip;
begin
ip_inst : ip port map ( io_bus_1 => int_bus, io_bus_2 => io_bus_2(7 downto 0), ctrl => en, ... );
int_bus_out