Hello folks,
I am trying to get a VHDL testbench running with the VHDL I2C core model. I am using spartan 6 fpga and using a simple state machine.
The problem with simulation result is that it is writing data properly but not reading it.I do not understand what is problem?
here is my testbench Data in sent internally via array.
ENTITY mainfiletb12 IS END mainfiletb12; ARCHITECTURE behavior OF mainfiletb12 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Main_file PORT( CLK_10_MHz : IN std_logic; ResetN : IN std_logic; SCL1 : OUT std_logic; --serial clock input SDA1 : INOUT std_logic; ---serial data Read_WriteN : IN std_logic;---read write bit 1 for read, 0 for write AddressIn : IN std_logic_vector(7 downto 0); --Register address Ack1 : OUT std_logic; --acknoledge bit DataOut1 : OUT std_logic_vector(7 downto 0); --output data StateOute : OUT std_logic_vector(7 downto 0); -- state register RegisterAddressOut1 : OUT std_logic_vector(7 downto 0) ); END COMPONENT;
--Inputs signal CLK_10_MHz : std_logic := '0'; signal ResetN : std_logic := '0'; signal Read_WriteN : std_logic := '0'; signal AddressIn : std_logic_vector(7 downto 0) := (others => '0');
--BiDirs signal SDA1 : std_logic;
--Outputs signal SCL1 : std_logic; signal Ack1 : std_logic; signal DataOut1 : std_logic_vector(7 downto 0); signal StateOute : std_logic_vector(7 downto 0); signal RegisterAddressOut1 : std_logic_vector(7 downto 0);
-- Clock period definitions constant CLK_10_MHz_period : time := 100 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Main_file PORT MAP ( CLK_10_MHz => CLK_10_MHz, ResetN => ResetN, BCLK => BCLK, LRCLK => LRCLK, SCL1 => SCL1, SDA1 => SDA1, Read_WriteN => Read_WriteN, SDIN => SDIN, AddressIn => AddressIn, Ack1 => Ack1, DataOut1 => DataOut1, Dataw => Dataw, StateOute => StateOute, StateOut3 => StateOut3, RegisterAddressOut1 => RegisterAddressOut1 ); -- Clock process definitions CLK_10_MHz_process :process begin CLK_10_MHz