Hello
The following is said in the documentation of Xilinx ISE (in th
following place for ISE users: /doc/usenglish/help/iseguide/iseguide.htm#html/fd_inst_bram_vhdl.htm)
The following VHDL code demonstrates how to infer a Dual Port BlockRA
component for Virtex? devices when synthesizing with XST. Only XS supports RAM inference
entity dpblockram is
port (clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(4 downto 0)
dpra : in std_logic_vector(4 downto 0);
di : in std_logic_vector(3 downto 0);
spo : out std_logic_vector(3 downto 0);
dpo : out std_logic_vector(3 downto 0));
end dpblockram;
architecture syn of dpblockram i
type ram_type is array (31 downto 0) of std_logic_vecto
(3 downto 0);
signal RAM : ram_type;
signal read_a : std_logic_vector(4 downto 0);
signal read_dpra : std_logic_vector(4 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') the
if (we = '1') then
RAM(conv_integer(a))