FPGA or CPLD

Try reading the data sheets

Here are a couple of links to glossary definitions that may help:

Most CPLDs are non-volatile. Most FPGAs are volatile and must be programed with each application of power, (requiring external logic and memory) though some use non-volatile ram.

CPLDs contain several PLDs and a programmable interconnect scheme. These PLDs are similar to the 22V10, a sum-of-products array, some muxes and flip-flops in a standardized organization.

FPGAs generally contain large arrays of gates or configurable logic blocks which can be progammably interconnected. FPGAs have logic specialized for I/O placed on the periphery of the chip with various schemes to optimize interconnection. FPGAs are also more likely to contain specialized elements. There are usually pre-configured design elements available for FPGAs such as multipliers, UARTS, microprocessors etc.

Choosing between the two can be difficult. FPGAs can run out of interconnect resources in a given area just like the CPLDs. In general a CPLD might implement a function that fits in one its PLDs more predictably than letting the compiler implement the function in an FPGA. Sometimes you have to weight parameters to force an FPGA compiler to place a function's elements close to one another. A CPLD's interconnect scheme is usually more static and predictable with regards to speed.

You can usually split elements in an FPGA between functions more easily than in a CPLD making for a denser implementation. Ignoring pin limitations, when you run out of resources in a CPLD you simply can't implement the design. When you put the same design in a similar sized FPGA you may still have plenty of resources, but a tough time getting it to run at speed because of delays across the chip.