Hello,
i want to create a special UART with a FIFO (at least 64 Bytes deep, perhaps bigger). Can someone tell me, how a FIFO can be implemented in hardware ? Is is "simply" an array of bytes, with two counters: one for filling it in and one for reading out ? Or is there a better approach ?
At the moment i have only knowledge in ABEL with XILINX CPLD (XC95) series. Is it the right way to use a CPLD (perhaps a big one, because of the amount of storage cells needed only for the FIFO) ? Or does a FPGA (i read they have RAM inside, where i hopefully can put my FIFO in ?) fit better this job ? What XILINX chip (because of already available environment) do you recommend for this and why ?
Regards and thanks for helping,
Martin