UART with FIFO -> CPLD / FPGA / ?

Hello,

i want to create a special UART with a FIFO (at least 64 Bytes deep, perhaps bigger). Can someone tell me, how a FIFO can be implemented in hardware ? Is is "simply" an array of bytes, with two counters: one for filling it in and one for reading out ? Or is there a better approach ?

At the moment i have only knowledge in ABEL with XILINX CPLD (XC95) series. Is it the right way to use a CPLD (perhaps a big one, because of the amount of storage cells needed only for the FIFO) ? Or does a FPGA (i read they have RAM inside, where i hopefully can put my FIFO in ?) fit better this job ? What XILINX chip (because of already available environment) do you recommend for this and why ?

Regards and thanks for helping,

Martin

Reply to
Martin Maurer
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Do a search, esp. of the FPGA/CPLD vendor web sites. FIFO examples abound. A FIFO is a homework assignment :)

Unless you're using one of the new Lattice XPLDs, you can't use a CPLD to do a FIFO using internal RAM, since CPLDs ('cept those Lattices) don't have internal RAM.

Pick one that has enough internal resources for your application. Any of the Xilinx (or Altera, or other brands) will do fine.

Reply to
Andy Peters

Check out the Picoblaze source code by Ken Chapman, which is available for free from Xilinx web site. The source included really nice and compact UART with 16-byte FIFO.

Remis

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Reply to
Remis Norvilis

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