GAL,PAL,PLD, CPLD,FPGA, (what else...?)

GAL : Generic Logic Array PAL : Programmable Array Logic PLD : Programmable Logic Device CPLD : Complex Programmable Logic Device FPGA : Field Programmable Gate Array

Can someone explain with comparison what is the difference between all these GAL,PAL,PLD, CPLD,FPGA, (what else...?) logic units?

Can all these units can be programmable with VHDL ?

Reply to
<many gates>
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wrote in news:4125f816$0$6317$

I thought this was: Gate Array Logic.

That's a language. As long as someone has a tool to convert VHDL source code to the device's expected "bit" file then yes.

- Mark ->
Reply to
Mark A. Odell

These are all PLDs. I'm not sure where the border is between SPLD (Simpled PLDs) and CPLDs. PALs were some of the first PLDs. There were also PLAs (Programmable Logic Arrays). These two were fuse programmable, you programmed them once. GALs (as far as I know) are PALs that use some form of non-volatile memory for the "fuse bits". I don't know if they use EEPROM or FLASH. At least a company I do work for switched from PALs to GALs and it was nice not throwing PALs away when we had to make a change.

I think of PALs and GALs are SPLDs; FPGAs as CPLDs.

But then, I'm a software guy. :-)

Reply to
Gary Kato

schrieb im Newsbeitrag news:4125f816$0$6317$ > GAL,PAL,PLD, CPLD,FPGA, (what else...?) >

Hello, As a long year digital expert I'll try to tell you the difference of all these logic parts. First: the content of all of them can be described by the language VHDL. But this makes sense only with higher complexities, which big CPLDs and FPGAs have. PLDs, PALs and GALs are the lowest complexity of logic arrays (f.e.

22V10 -> 10 Flip-Flops + AND/OR-Logic). CPLDs and FPGAs have more gates and Flip-Flops, where CPLDs have a more fixed structure (predefined number of gates and FFs) , while FPGAs are consisting sometimes of pure gates (ACTEL, Antifuse) and can be handled like true gate arrays. FFs are built by gates then. For the high complexities VHDL is the right tool to handle big designs. But you should keep in mind, that the later layout of the FPGA-chip depends on the design (how many IO-ports, number of FFs, number of gates, number of logic blocks etc.). The best way to learn about the digital designs is to use the partly free tools and do a design by yourself. All suppliers have nice kitparts and offer design software .

Have fun.

Regards, Roland

Reply to
Roland Macho

Dear Roland,

Thank you for your clear and easy to understand summary.


Can you recomment a particular one to learn CPLD/FPGA and VHDL?






Reply to
<many gates>

I have a simple CPLD design on my webs site that may be used with the free Xilinx Webpack software.


Leon Heller, G1HSM
Reply to
Leon Heller

Thank you all.. Leon's page about CPLD,FPGA etc on

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contains a good summary about these units.

Reply to
<many gates>

When I see those terms (which is probably NOT how Marketing sees them) I differentiate between SPLD and CPLD by the presence of an interconnect matrix that is distinct from the sum of product terms matrix within a logic block.

An SPLD has goes-ins and goes-outs with a sum of product term matrix connecting everything to everything. A CPLD is two or more SPLDs wired together with an interconnect matrix that is mostly wires, not gates.

An FPGA, on the other hand, distributes many more registers more or less uniformly throughout the device, associating each register with a relatively (to CPLDs) simpler selection of logic and, often, a small amount of RAM.

Some designs can be realized in either a CPLD or an FPGA. However, register-heavy or RAM-intensive designs (e.g. a microcontroller core) are more appropriate to an FPGA. Address decoding, data latches, and replacing handfuls of glue logic chips with a single device are more appropriate to a CPLD.

Rich Webb   Norfolk, VA
Reply to
Rich Webb

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