FPGA vs CPLD

It's getting very blurred. Altera's new CPLD, the MAX II, is really an FPGA, apparently.

Leon

Is this a serious question? The internal architectures are very different, go download the architecture documents from the Xilinx site. From an application standpoint FPGAs are much much bigger than CPLDs. CPLDs are used for very simple glue logic applications, they are cheap and nonvolatile. FPGAs can implement very complex systems, but they are more expensive on a per package basis although they are much cheaper on a per gate basis. FPGAs require some support logic to initialize them, either a serial prom or an interface to a CPU (frequently implemented with a CPLD).

The common understanding is that CPLDs are EEPOM or Flash based and have to be programmed once. They have up to say 512 Flipflops. FPGAs on the other hand are RAM based, meaning they have to be programmed at every powerup. This usually happens with a small external Flash, a CPU or whatever. The smallest FPFA is far bigger than the biggest CPLD.

Hope that helps.

Rene

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General logics vs. Simple reg/decoder Expensive ($10 - $20) vs. Cheap ($1 - $2) Big (> 100 pins) vs. Small (> 44 pins)

...

10 years ago, things were relatively simple : FPGA's were pretty much all RAM/loader designs, with low power, and granular logic. CPLDs were were higher power, fast with wide-logic terms, and limited in register count.

These days, there is much more overlap and bluring of the lines.

# Some FPGAs are FLASH (Lattice, Actel) # Some CPLDs have granular logic ( MAX II ) # Some CPLDs have RAM/Loader built in ( MAX II, Coolrunner... ) # For lowest static power, modern CPLDs are

How about an FPGA which looks like a CPLD (in programming terms) No boot prom or external logic, instead this has internal eeprom.

CPLDs are most often used for less datapath intensive timing-critical designs (i.e. more control-path like stuff), while FPGAs are fine for highly datapath intensive designs.

FPGAs are rather easily scalable. That is, they have a structure comparable to US-like (i.e. "constructed") cities. You have a very regular grid with buildings (i.e. logic blocks) as well as horizontal and vertical streets (i.e. the connections). You can easily extend the structure at the borders.

CPLDs have a completely different structure. Mostly, there is a centralized connection structure and the logic elements are grouped around it. Thus, the analogy is something like a farm. You can recognize easily that such a design does not scale very well. Because of that, the CPLDs have a rather small capacity when compared to FPGAs. However, they have the big advantage of a predictably fast interconnection. I.e. it does not matter where the logic elements are positioned - the delay of the connections between them is almost the same. This is not the case for FPGAs. There, the farther the elements are away from each other, the higher the delay.

Besides this difference, CPLDs have mostly much more powerful logic elements than FPGAs. This also attributes to the use of CPLDs especially for control paths.

Another difference that has been already cited by others is typically the non-volatile nature of CPLDs and the volatile nature of FPGAs.

Regards, Mario

I use Fpgas in 84cqfp while I have just read, that Altera ships its new MaxII CPLD in up to 324 pin BGA. I think the first point ist the best way to differ between CPLD and Fpga.

bye Thomas

That's pretty wrong. Actel has flashbased Fpgas (and antifuse based).

The main difference is that CPLDs are mainly focused on Input->(fast)Logic->Register->Output while Fpgas are typically slower for CPLD tasks, but have more configuration possibillities and support more complex logic structures. A typical CPLD design would have fast but simple operations while a fpga has complex operations based on many internal registers.

bye Thomas

Another point blurring the line between FPGA and CPLD is pin-to-pin speed. 10 years ago an FPGA was clearly not suited to fast asynchronous designs. Modern FPGA's, while not as fast as the fastest modern CPLD are often fast enough for functions like address decoding and asynchronous memory interface.

Also you will find both FPGA's and CPLD's with programmable I/O standards (LVTTL, LVCMOS, SSTL, HSTL, LVDS...)

Price per gate is still less in FPGA, but the overall price range now overlaps considerably.

Still:

if the design is static and fits in a CPLD, you're probably going to get off cheaper with a CPLD.

if the design requires instant-on you're again probably better off with a CPLD, although a few FPGA's have this feature.

if the design requires flexibility to download different logic depend> > Hello,

Lets take an example and see what the concensus is:

Gate Count: 40K ASIC gates Speed: 50 MHz PinOut: 100 pins Other: ???

One Configuration: Spartan-III would be a suitable fit with $20 price tag (scaling to $10 with volume) + $3 prom.

Altenatives from Altera? Actel (may be anti fuse?)

Could some one fill in...

-Rajeev

Where is the relation with my posting?

Mario

True, Flash FPGAs blurr the line. However according to the data I have available some of your statements are also not correct. The fastest CPLD I came across does in the order of

220 MHz, and has no internal multiplier. Whereas the FPGAs, at least the more modern ones tend to have clock multipliers and 220 MHz is not considered fast at all.

Rene

Mario,

I was trying to being up an example so that we could see which techonlogy from which vendor makes best sense. This happens to be a design I worked in the past.

-Rajeev