GAL,PAL,PLD, CPLD,FPGA, (what else...?)

GAL : Generic Logic Array PAL : Programmable Array Logic PLD : Programmable Logic Device CPLD : Complex Programmable Logic Device FPGA : Field Programmable Gate Array

Can someone explain with comparison what is the difference between all these GAL,PAL,PLD, CPLD,FPGA, (what else...?) logic units?

Can all these units can be programmable with VHDL ?

Reply to
<many gates>
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wrote in news:4125f816$0$6317$

I thought this was: Gate Array Logic.

That's a language. As long as someone has a tool to convert VHDL source code to the device's expected "bit" file then yes.

- Mark ->
Reply to
Mark A. Odell

schrieb im Newsbeitrag news:4125f816$0$6317$ > GAL,PAL,PLD, CPLD,FPGA, (what else...?) >

Hello, As a long year digital expert I'll try to tell you the difference of all these logic parts. First: the content of all of them can be described by the language VHDL. But this makes sense only with higher complexities, which big CPLDs and FPGAs have. PLDs, PALs and GALs are the lowest complexity of logic arrays (f.e.

22V10 -> 10 Flip-Flops + AND/OR-Logic). CPLDs and FPGAs have more gates and Flip-Flops, where CPLDs have a more fixed structure (predefined number of gates and FFs) , while FPGAs are consisting sometimes of pure gates (ACTEL, Antifuse) and can be handled like true gate arrays. FFs are built by gates then. For the high complexities VHDL is the right tool to handle big designs. But you should keep in mind, that the later layout of the FPGA-chip depends on the design (how many IO-ports, number of FFs, number of gates, number of logic blocks etc.). The best way to learn about the digital designs is to use the partly free tools and do a design by yourself. All suppliers have nice kitparts and offer design software .

Have fun.

Regards, Roland

Reply to
Roland Macho

manygates asked:

This could take awhile :)

The most basic thing all of these have in common is the ability to create unique circuit configurations on a standard device, and with most, the ability to erase these configurations, and create new ones. If we had a time machine to go back - way back, we would find only devices with fixed architecture elements, e.g. SSI devices(small scale integration) andgates(7408) nandgates(7400), or gates (7432) inverters (7404) and then a big jump to MSI (medium scale integration) like 7474(d flipflop with set/reset) counters (74161

- 4bit counter) , and the industry continues into LSI, VLSI, ASICs, uprocessors, memories, etc....

then this idea of PLD - programmable logic device by using fuses in an array, speicific configurations can be accomplished- by connecting traces in the metal layers on a device, making the gates connected to them form new circuits - unfortunately, fuses only work once :) - testing by the manufacturer was limited - after all, how do we test a fuse?

PAL programmable array logic early PALS were in preset configurations - where fuses could acitivate some customization - the pal16l2, the pal16r4, had and/or gate structures, or limited registers to certain points - somewhere along the way - UVerasable arrived, displacing one time programmable fuses - with a nice quartz window, so you could flood the connections with UV to reset the programming cell - and use a nice paper label to cover it up when programmed - and with UV, testing by the manufaturer improved, as a pattern could be built, then removed, although with 30-60minute erase times, it was still limited -

GALs - neat concept - all possible PAL configurations could be accomplished,e.g., 16v8 - Variable function, as the 'macrocell' for each output pad had both combinatorial and registered capability, and even better, these werre electrically erasable(EECMOS) and could easily be tested and erased in milliseconds

Along came FPGA and CPLD

I know I am leaving out a bunch of detail - the various vendors do a superb job of describing in detail in their literature -

CPLD - Complex Programmable Logic Device early CPLD structures were closely related to the GAL/PAL idea, and created an array of PALs ( think LAB, or GLB, or PALblock, or functionblock) in various sizes and what not - CPLDs at their most basic are this A COMPLEX LOGIC BLOCK - with anywhere from

36 to 68 inputs available per block, with a range of PTERMS(and gate) from 1 to 160, available to drive each macrocell - combinatorial or registered. Mostly NONVOLATILE devices(EECMOS) with some newer devices also incorporating SRAM as part of the architecture, decent clock structures, high performance for large, single logic level functions - think statemachines, decoders, counters etc - Routing and interconnect is typically a single large central routing array - so interconnecting logic has little penalty in routing - and within the LOGIC BLOCK - there is full interconnect for the various elements

FPGA Field programmable Gate Array - FPGAs are devices which can achieve significantly larger logic gate counts, with each logic element TYPICALLY being built with a 4input LUT(look up table - which allows pretty much any combination of 4 inputs ) with a combinatorial and/or registered output available per logic element - each vendor has thier own 'tweek' on this with additinal logic for muxes, carrychainsfor arithmetic/ counting functions, etc -I'm sure others will jump in here) - nad since the logic element is small, a lot more fit on a device!. To interconnect these logic cells requires significant routing, or interconnect, resources, to build a larger function out of the many small functions. Much magic is required here, by the silicon designers to balance resource requirements, and the SW designers, to implement algorithms which efficiently connect the elements together. FPGAs generally offer additional elements, e.g. RAM BLOCKS, so that more complex system functions can be implemented within the single device. As technology has moved forward, many different elements have found their way into FPGA - processors, SERDES, DSPBLOCKS etc.

MOSTLY based on SRAM processes, they offer rapid reconfigurability as well, with the burden of storage somewhere in the system for the datastreams required to configure the device. There are Vendors with NONVOLATILE FPGAs as well, running form FUSE BASED(one time programmable) to Flash and eecmos based devices which incorporate flash and eecmos memory to carry the datastream for configuration on chip.

I hope this was a good start - Peter, Paul, Austin, Jim, Rick, Ray, Uwe, any others out there want to expand on these points?

Mike Thomas Lattice SFAE NY/NJ

Reply to

Dear Roland,

Thank you for your clear and easy to understand summary.


Can you recomment a particular one to learn CPLD/FPGA and VHDL?






Reply to
<many gates>

I have a simple CPLD design on my webs site that may be used with the free Xilinx Webpack software.


Leon Heller, G1HSM
Reply to
Leon Heller

Thank you all.. Leon's page about CPLD,FPGA etc on

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contains a good summary about these units.

Reply to
<many gates>

Dear Mikeandmax

THANK YOU VERY MUCH for your very valuable posting. I've enjoyed reading it and learnt alot in few paragraphs.









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superb job

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Reply to
<many gates>

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