Latest threads in Field-Programmable Gate Arrays

Using the Xilinx JTAG Interface as a General-Purpose Communication Port

For anyone interested in using the Xilinx JTAG Interface as a General-Purpose Communication Port see http://www.xilinx....

1 21yrs

bob.allen

1 21yrs bob.allen

Xilinx EDK tool flow

Please bear with me, I am just learning how to use EDK... It seems nice, but sort of self-contained. All of the example...

2 21yrs

mbmsv

2 21yrs mbmsv

FPGA programming via Slave-Serial-Mode

We are programming an FPGA (Spartan2E) via a CPLD in Slave-Serial-Mode. The CPLD loads the bitfile from FLASH and write...

4 21yrs

c.jesko

4 21yrs c.jesko

exp(-x) function

I'm new to math function on FPGA, but I need to calculate exp(-x) wit a Spartan3 in fixed point 16bit numbers. How can...

4 21yrs

andpaoli

4 21yrs andpaoli

Driving two DCM with same clock input pad.

Hi everyone, I am using a demo board from Memec whose clock source is given to one of the input PINS of the FPGA. I hav...

6 21yrs

vasus_ss

6 21yrs vasus_ss

Coregen to generate a ROM of 32X1500 using LUT to construct multiplexer.

When I choose Distribute Memory -> Depth 2048 -> Width 64 -> ROM -> LUT based, and my .coe file contains only 1500 word...

1 21yrs

invalicd

1 21yrs invalicd

Spartan II-e PCB

hello, I'm about to layout a circuit for a pcb that includes the Xilinx spartan II-e and external circuitry (simple int...

1 21yrs

aosik5

1 21yrs aosik5

hook up SRAM to Spartan3

Hi, Has anyone successfully hooked up an SRAM to the Spartan3 FPGA yet?? If you have, can you tell me how you hooked it...

6 21yrs

ann.lai

6 21yrs ann.lai

Dividing a 24 bit std_logic_vector by a decimal number

Hi, Is there anywayz a 24 bit std_logic_vector can be divided by a decimal number (eg: 1.36)using VHDL. The quotient ne...

12 21yrs

genlocks

12 21yrs genlocks

Looking for an FPGA blogger

Hi all. I'm looking for a blogger for the new Chip Design blogsphere. The potential candidate will have to meet these t...

0 21yrs

jblyler

0 21yrs jblyler

Altera MAX2 optimized serial RISC interim source code files released

Hi http://wiki.openchip.org/index.php/OpenChip:PicoMax there is description of what is implemented and working http://g...

0 21yrs

antti

0 21yrs antti

Custom compilation step in Quartus

Hi y'all : We create our .mif files by running a custom analysis program on a set of data files. I'd like to include th...

2 21yrs

xxx

2 21yrs xxx

ISE 6.3 sp3 - PAR result strange

I have a top level schematic includes several macro instants (SDRAM controllers and others stuff) the design target spa...

0 21yrs

looking for keyboard scancode

Hi, As I am making a PS/2 keyboard vhd , I am looking for scancodes of an azerty keyboard to convert code from keyboard...

4 21yrs

kclo4_NO_SPAM_

4 21yrs kclo4_NO_SPAM_

ISE

hi, in ise, the console window says "synthesis completed" but in the process for source, it still shows a question mark...

4 21yrs

mmkumar

4 21yrs mmkumar

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