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Driving two DCM with same clock input pad.

Hi everyone, I am using a demo board from Memec whose clock source is given to one of the input PINS of the FPGA. I have to generate two clocks of different frequency from this input clock source. I am using two DCM's for these. When i give the input clock to both the DCMs there is an error during implementing the design which says one input clock cannot drive two DCM's or something like that. So i tried giving the output of one of the DCM's to the input of another DCM. Even then it gives an error during the implementation stage. Both the error cases are mentioned below.

This problem has been addressed before in this group without any possible solution. But it has been a long time. So i was thinking anyone has come up with an idea. I have also opened a webcase with Xilinx. The first case is when the input clock is given as an input to both the DCM's The second case is when the output clock of the DCM is given as an input to the second DCM.

case1 ERROR:LIT - IPAD symbol "clkin" is driving more than one loads. IPAD can only drive a single IBUF or two IBUFDS. If you are using a BUF instead of an IBUF, it may have been simplified, please use an explicit IBUF instead. Errors found during logical drc.

case2

ERROR:NgdBuild:455 - logical net 'CLK0_OUT' has multiple drivers. The possible drivers causing this are: pin O on block dcm_33_CLK0_BUFG_INST with type BUFG, pin PAD on block CLK0_OUT with type PAD ERROR:NgdBuild:466 - input pad net 'CLK0_OUT' has illegal connection. Possible pins causing this are: pin O on block dcm_33_CLK0_BUFG_INST with type BUFG Thanks and regards

Reply to
design
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Dear Design, Having trouble living up to your name, I see. Why not do what the error message tells you? The ISE software authors went to all that trouble to write 'please use an explicit IBUF instead' and then you go and ignore them. ;-) Cheers, Syms.

Reply to
Symon

Your problem is being caused because you are trying to drive two IBUFG's from the same pad. IBUFG's are special clock buffers that are connected directly to certain FPGA dedicated clk pins to provide a very low delay path to a DCM. Since there is a dedicated connection between the pin and the IBUFG, it is impossible to drive two IBUFG's from the same pin (this seems to be what you are attempting to do). The solution is to use only one IBUFG and use the output from this to drive the two different DCM's.

Cheers Sam

Reply to
Sam

I see two potential problems with what you are trying to do.

  1. As mentioned before you can only drive one IBUF/IBUFG from a Pad.
  2. Outputs of two DCMs from same reference clock can have a phase offset. I am not sure of your applicati> Hi everyone,

the

Reply to
skherich

The V2Pro spec's a max of +/-140 ps (so I guess that's really 280 ps) of phase offset between DCM's, which I wouldn't think would be a problem for most designs running at reasonable clock rates. Although it isn't stated, I believe this phase spec only applies when using CLK0, CLK180, CLK90, CLK270, CLK2X, and CLK2X180. The phase of the divided outputs (CLKDV OR CLKFX) can not be controlled.

Have fun,

Marc

Reply to
Marc Randolph

Thanks for all the replies. I did finally manage to fix it. All i needed to do was select the clock source as internal for one of the DCM. Although i understood the part where I needed to use an explicit IBUF or IBUFG i am not sure on how to do it. I tried instantiating the IBUF or IBUFG module and using the output to drive the DCM's.

Regards

Reply to
design

explicit

the

It's pretty simple to instantiate the IBUFG's explicitly. The code below drives two DCM's from a single IBUFG. You will have to include the unisim.vcomponents package for ISE to recognise the DCM and IBUFG primitives, but if you're using DCM's you've probably figured this out already.

Sam

IBUFG1 : IBUFG port map (O=>clk_ibufg,I=>pad_clkin);

DCM1 : DCM port map( CLKIN=>clk_ibufg,CLKFB=>internal_clk1, DSSEN=>'0',PSINCDEC=>'0',PSEN=>'0',PSCLK=>'0', RST=>'0',CLK0=>internal_clk1_bufg, CLK90=>open,CLK180=>open,CLK270=>open, CLK2X=>open,CLK2X180=>open,CLKDV=>open, CLKFX=>open,CLKFX180=>open, LOCKED=>open,PSDONE=>open, STATUS=>open);

BUFG1 : BUFG port map (O=>internal_clk1, I=>internal_clk1_bufg);

DCM2 : DCM port map( CLKIN=>clk_ibufg,CLKFB=>internal_clk2, DSSEN=>'0',PSINCDEC=>'0',PSEN=>'0',PSCLK=>'0', RST=>'0',CLK0=>internal_clk2_bufg, CLK90=>open,CLK180=>open,CLK270=>open, CLK2X=>open,CLK2X180=>open,CLKDV=>open, CLKFX=>open,CLKFX180=>open, LOCKED=>open,PSDONE=>open, STATUS=>open);

BUFG2 : BUFG port map (O=>internal_clk2, I=>internal_clk2_bufg);

Reply to
Sam

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