Altera MAX2 optimized serial RISC interim source code files released

Hi

there is description of what is implemented and working

file snapshot download is there

I am releasing it as I possible cant get it finished in a very short time, so presenting a snapshot as it is. It could already serve as example of an bit serial processor implementation

the processor including instruction set is optimized to be executed from MAX2 UFM memory doing on the fly decoding.

for Xilinx SRL16 optimized bit serial processor the architecture and command set would be different.

the snapshot includes a ISE project with UFM model ready to be simulated in ModelSim

Antti would be happy to hear any comments and suggestions!