Xilinx EDK tool flow

"MM" schrieb im Newsbeitrag news: snipped-for-privacy@individual.net...




1) create a user logic EDK core and add the connections in the XPS/EDK or 2) use the EDK generated system as submodule in ISE project


Reply to
Antti Lukats
Loading thread data ...

Please bear with me, I am just learning how to use EDK... It seems nice, but sort of self-contained. All of the examples and documentation show how to create a processor based system from start to generating a *.bit file, which is great, but what if I need to have some other unrelated logic in the FPGA? What should my tool flow be in that case? Also, how do I approach a project (from the tool flow viewpoint) with more than one processor core?

Thanks, /Mikhail

Reply to

You can choose to make it a completely self contained EDK project, and I have done one project that way. But I have since moved to embedding the processor/EDK portion in a plain old VHDL project and compiling that with ISE, which I guess Xilinx calls a "ProjNav" implementation flow. I mainly find this a little easier during the design and simulation portion of the project, which is of course the longest phase of a project. EDK adds another layer of stuff to deal with, and I eventually found it to be a minor annoyance, but that is probably just a personal preference.

The one thing I found important to do for this approach was that I implemented a generic register interface for EDK, which allows me to implement the actual registers outside of EDK. Without that step, every time I created a new register with new inputs/outputs, I basically had to rerun EDK. Now, I rarely run the EDK compile, since almost everything I am changing during the design phase is outside the EDK portion.

Reply to
Duane Clark

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.