ISE 6.3 sp3 - PAR result strange

I have a top level schematic includes several macro instants (SDRAM controllers and others stuff) the design target spartan3-1000, speed-4. So far I haven't constraint pin LOC yet, but the SDRAM clock is constrainted at 166 Mhz. It's strange if I let the ISE "auto assign" the Inst. name as XLXI_xxx... for the the macros (specially the sdram controllers) then it pass 166 MHZ easily. If I manually assign the name likes the old style (U1, U2, U3....) then it FAILED the clock constraint, and it is consistent !!! So, the quesion is what's going on...I may learn something here but still dont understand WHY.... Anyone know? please.....