Field-Programmable Gate Arrays

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ISE

hi, in ise, the console window says "synthesis completed" but in the process for source, it still shows a question mark...
4 comments posted 21yrs
posted by mmkumar
4 comments posted 21yrs posted by mmkumar

Quartus II 4.1 Problem

Hi folks, I'm facing one problem that is driving me crazy... The error is the following: Error: JTAG ID code specified...
5 comments posted 21yrs
posted by jmartins
5 comments posted 21yrs posted by jmartins

newbie verilog question

In reference to the following code snippet: always @(posedge ata_dior) begin dout = mem[ addr ]; dout_en = 1; end alway...
5 comments posted 21yrs
posted by markm
5 comments posted 21yrs posted by markm

Xilinx- Extract a pin layout

Hi- I am in the midst of bringing a Xilinx design to the lab. It is in a larger BGA package and is becoming hard to pro...
6 comments posted 21yrs
posted by wpiman
6 comments posted 21yrs posted by wpiman

What type of IO to use

I bought the Digilent XC2 board (Xilinx CoolRunner II XC2C256 TQ144) a while back for electronics hobby stuff and I was...
5 comments posted 21yrs
posted by no
5 comments posted 21yrs posted by no

C++ code to FPGA

I do not have FPGA experience, and I am not sure if my question make sense. Assume that we have a set of C++ code of va...
4 comments posted 21yrs
posted by <Ustuiosima Huslova>
4 comments posted 21yrs posted by <Ustuiosima Huslova>

using (verilog) reg as memory

Hi Someone must have ask this question before. Is it a good idea to use verilog's reg to declare a large block of memory...
5 comments posted 21yrs
posted by paulw
5 comments posted 21yrs posted by paulw

How do I fix this error?

I am using NCVerilog and Virtex2-6000. I tied RST pin of the DCM1 to 1'b0 in RTL code. RTL simulation was all right, bu...
0 comments posted 21yrs
posted by Sea.Squid
0 comments posted 21yrs posted by Sea.Squid

Spartan 3, Microblaze and FPU

Folks, I'm looking at a design problem that may need a floating point unit (single precision is fine). Part of the unkn...
2 comments posted 21yrs
posted by oth3ll0
2 comments posted 21yrs posted by oth3ll0

Block RAM in Xilinx Spartan 3

I get this message when i synthesize my code "you may be trying to describe a RAM in a way that is incompatible with bl...
3 comments posted 21yrs
posted by bhaskarstays
3 comments posted 21yrs posted by bhaskarstays

Re: A newbie question (Xilinx or Altera Env?)

>Hello, >I am interested in learning fpga. I want advice on which software/HW dev >board should I pick. I have download...
0 comments posted 21yrs
posted by philip
0 comments posted 21yrs posted by philip

User I/O via Altera MAX7000S JTAG?

Is there any way to use the JTAG pins of an EPM7128S for user I/O, without permanently commiting them as I/O and thereb...
4 comments posted 21yrs
posted by andrew
4 comments posted 21yrs posted by andrew