Field-Programmable Gate Arrays

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Saturating an integer

Hi, Firstly, I'm a newbie at VHDL. I'm using 2 constants to derive a valid range of system clock periods: constant ENC_...
7 comments posted 21yrs
posted by dave_baker_100
7 comments posted 21yrs posted by dave_baker_100

Availability of the Xilinx ML481 Development Board

During the latest Xilinx netseminar on Power the Xilinx ML481 board was mentioned as a good way for users to evalute th...
5 comments posted 21yrs
posted by kbrown_home
5 comments posted 21yrs posted by kbrown_home

embedded linux for v2pro PPC?

Hello I noticed the University of Queensland distribution of uClinux for the Xilinx Microblaze soft processor core. Doe...
5 comments posted 21yrs
posted by padudle
5 comments posted 21yrs posted by padudle

New Altera Software Dev Board with VGA full color?

What is this? http://www.altera.com/corporate/cust_successes/customer_showcase/csh-seventech_lp.html With VGA - LAN - I/...
0 comments posted 21yrs
posted by Robert_zip
0 comments posted 21yrs posted by Robert_zip

Gated clock problem

I posted following message, but nobody respond(I don't know the reason, maybe it is too naive). I I post it here again,...
12 comments posted 21yrs
posted by fwj
12 comments posted 21yrs posted by fwj

ERROR: NgdBuild:604 - logical block

Hi all: I am trying to add customized IP to microblaze using FSL channel. The customized IP includes block ram generate...
2 comments posted 21yrs
posted by aroutchelvame
2 comments posted 21yrs posted by aroutchelvame

Altera Excalibur EBI problem

BlankHi, I seem to have a problem talking to a MAC chip that is connected as a memory mapped device on the EBI bus of a...
3 comments posted 21yrs
posted by bta3
3 comments posted 21yrs posted by bta3

Simulating custom peripherals

Any pointers or advice on simulating a peripheral created by the wizard in Xilinx EDK? I started this thing a while ago...
6 comments posted 21yrs
posted by joeylrios
6 comments posted 21yrs posted by joeylrios

VHDL help with adding modules

Hey guys, I'm fairly new to vhdl. Trying to test a small portion of an mp3 player to work. Seems that If I add my synch...
3 comments posted 21yrs
posted by walterwang
3 comments posted 21yrs posted by walterwang

Multiply Accumulate FPGA/DSP

I have been tasked with trying to implement a FFT algorithm in a FPGA/DSP architecture. The algorithm would be a N poin...
15 comments posted 21yrs
posted by larsonbr
15 comments posted 21yrs posted by larsonbr

Negative hold time from Quartus

Hi, I am using Synplify Pro for synthesis and Qurtus for remaining steps. In my design , I am using the filp-flop outpu...
1 comments posted 21yrs
posted by am.imak
1 comments posted 21yrs posted by am.imak

DCM, constraints and routing (Xilinx Spartan 3)

Hi everyone, On a Spartan 3, I would like a single clock-signal to drive the inputs of all 4 DCM's. How would I get a c...
2 comments posted 21yrs
posted by p.boven
2 comments posted 21yrs posted by p.boven

Max freq. of operation in FPGA?

Hi all, After synthesis if i get the following timing report then what will be my frequency of operation Minimum period...
3 comments posted 21yrs
posted by Puneetsingh81
3 comments posted 21yrs posted by Puneetsingh81

Memec/Insight LX25LC Board Flash Troubles

Hi, just wanted to check if somebody here had any luck programming the flash (AT45DB161B) on the Memec/Insigth developm...
0 comments posted 21yrs
posted by russelmann
0 comments posted 21yrs posted by russelmann

JTAG without parallel port

I have a Xilinx Spartan 3 board, and comes only with the parallel JTAG cable. My big problem is that any of my computer...
3 comments posted 21yrs
posted by rafaelgonzalez
3 comments posted 21yrs posted by rafaelgonzalez