Saturating an integer

May 04, 2005 7 Replies

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dave_baker_100 21 years ago

Hi,

Firstly, I'm a newbie at VHDL. I'm using 2 constants to derive a valid range of system clock periods:

constant ENC_FREQ_MIN : integer := 200; -- 200 Hz constant ENC_FREQ_MAX : integer := 3500; -- 3500 Hz constant ENC_PERIOD_RANGE : integer := 50e6 /(ENC_FREQ_MAX - ENC_FREQ_MIN); -- 50MHz system clock

I chose integers as I want the freedom to enter real frequencies rather than specifying bit array strings and working out their size plus I need to difference successive encoder periods to give +ve & -ve values

My problem is that I want a monitor signal which outputs the encoder period difference but only the lower order bits up to 8 bits, any greater than that I just want the 8 bit output to saturate.

How I can easily convert this difference (that has "unknown" size) to a saturated 8 bit number (+/-7 bits) ?

Thanks in advance Dave

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Symon 21 years ago

Is this OK? if difference > 255 then saturated

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dave_baker_100 21 years ago

Thanks! My application will do checks for < -128 & > 127 but the 'mod' is exactly what I need.

Thanks also for the VHDL newsgroup suggestion.

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Symon 21 years ago

No worries Dave. I also recommend

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

and stay clear of the other libraries.

This is a great starting point:-

formatting link

Yer man Jim knows his stuff!

Cheers, Syms.

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dave_baker_100 21 years ago

Symon - thanks for that little gem!

I have a couple of off-subject questions you may be able to answer:

1) Are there any really good books that relate VHDL to FPGA synthesis ?

2) Are there any rule-of-thumb measurements for the max. no. of lines of code in a clocked process statement ?

Many thanks Dave

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Ben Twijnstra 21 years ago

Hi dave,

My personal rule of thumb is that I should be able to cram a single process on a page of A4 paper when printed in 8-point courier. But, sometimes the algorithm just won't let you do this. In that case, put page breaks into the source code at strategic points, such as the after an end if, end case and stuff like that.

Best regards,

Ben

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JJ 21 years ago

1) Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog by Douglas J. Smith

gets mentioned alot

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Symon 21 years ago

Try getting on a course at Doulos. You used to get a free 'VHDL Golden Reference Guide'. V. useful. There a chap called Jonathan Bromley who posts here who's associated with them, he might be able to advise you on how to find out when the next course is, etc. Best, Syms.

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