Hi,
Firstly, I'm a newbie at VHDL. I'm using 2 constants to derive a valid range of system clock periods:
constant ENC_FREQ_MIN : integer := 200; -- 200 Hz constant ENC_FREQ_MAX : integer := 3500; -- 3500 Hz constant ENC_PERIOD_RANGE : integer := 50e6 /(ENC_FREQ_MAX - ENC_FREQ_MIN); -- 50MHz system clock
I chose integers as I want the freedom to enter real frequencies rather than specifying bit array strings and working out their size plus I need to difference successive encoder periods to give +ve & -ve values
My problem is that I want a monitor signal which outputs the encoder period difference but only the lower order bits up to 8 bits, any greater than that I just want the 8 bit output to saturate.
How I can easily convert this difference (that has "unknown" size) to a saturated 8 bit number (+/-7 bits) ?
Thanks in advance Dave