1. Home
  2. Field-Programmable Gate Arrays
  3. DCM, constraints and routing (Xilinx Spartan 3)

DCM, constraints and routing (Xilinx Spartan 3)

Hi everyone,

On a Spartan 3, I would like a single clock-signal to drive the inputs of all 4 DCM's. How would I get a clock-signal from the bottom to the top edge of the die, preferably with as little extra jitter as possible?

I would like to use all 4 DCM's to shift the input signal by a different amount (say 45/4 = 11.25 degrees, ). But do I need to use a BUFG to 'feedback' these signals back to the DCM? There's no real 'delay' that I want to counter, I'm trying to (ab)use the FPGA as a phase discriminator.

Secondly, I would like to have the four DCM outputs (0, 90, 180 and 270) each end up on the D-input of a flip-flop. Propagation delay on these paths should be small, but it is even more important that the signals arrive at their flip-flops simultaneously, or as much as possible. How can you enter that kind of constraint?

There are not enough BUFG(MUX) resources to have all 4 I/Q-phase outputs of all 4 DCM's run over them. So I'm thinking of not using the BUFGMUX for that at all, but simply placing my flip-flops close to their associoated DCMs. Is there any information available on how I can connect to the DCM outputs (long-lines? hex-lines? neighbours?). What position relative to the DCM should the 4 FF be at for equal delay?

When I've synthesized a design, I can see where it has placed all the resources. But is there any way to see how the actual routing of the signals over the FPGA is being done, what kind of lines are being used?

That's enough questions for one posting, I hope someone out there is kind enough to help me along a bit.

Regards, Paul Boven, PE1NUT Another FPGA-hobbyist

Reply to
Paul Boven
Loading thread data ...

Never had a case where I wanted all DCM to have same source but Why not connect the input source to all 4 input clock on the board so all 4 DCM get the same clock, you might want to use clock distributor and equal trace or any other technique but this way you can get the input clock of all DCM to be as closest as you can. To send a signal across the FPGA you can use either the Global clock or low skew lines. In global clock it mean most likely in your case after the DCM and the drawback is that you cascade DCM and this have its own problem of jitter and such. As for the feedback this come from either x1 (or x2 if you use x2) and not from the shifted phase output

0 and 180 do not need to have two output if they go to FF as you can always use the inverted prior to the FF in the CLB, and this you simple get by writing negedge instead of posedge. Same go to 90 and 270, use the 90 and negedge it for 270. As for not using BUFG you can do it and if the design is simple (small) and not "too fast" there is more than good chance the tool will be able to do it for you without your intervention. So I would suggest try it first and only if it fail look on the report and than you can move the FF and locate them where you want. As for looking I assume you look on the floorplaner, try looking also in the FPGA editor. Have fun.
Reply to
Berty

Dear Paul,

I never had anything like this in my designs, but...

First, you HAVE to use BUFG on the feedback clock, otherwise, the tool cannot automatically infer the deskewing function of DCM (I am not 100% sure about this, Xilinx guys are to ask), and this is what you have to do if you want to eliminate any delays in routing a clock from one edge of the FPGA to another.

Second, I do not think that there is any constraint covering what you want to do here. You would probably have to do this manually.

Is the clock slow enough to first multiply is and run some counter, whose bits will represent different phases? or if it is high, still can you multiply by 2/3/4 and use both some DCMs with phase outputs and less BUFGs?

hope this helps.

regards, Vladislav

Reply to
Vladislav Muravin

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.