Field-Programmable Gate Arrays

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Re: Force sequential assigment

Hi, If you have the following code: if (count < 255) begin en_ram
0 comments posted 21yrs
posted by ann.lai
0 comments posted 21yrs posted by ann.lai

Force sequential assigment

Hi, If you have the following code: if (count < 255) begin en_ram
4 comments posted 21yrs
posted by ann.lai
4 comments posted 21yrs posted by ann.lai

200+ MHz through a SCSI cable

Hi, I am glad to tell you, that my LCD via LVDS works now :) However it works only up to a lvds clock rate of about 200...
9 comments posted 21yrs
posted by benjamin
9 comments posted 21yrs posted by benjamin

writing with impact to eeprom

Hi, I want to write my bitstream into the eeprom of my V2 Board. In my jtag chain in impact a xcf04s gets listed. Howev...
2 comments posted 21yrs
posted by benjamin
2 comments posted 21yrs posted by benjamin

Performing Readback from Impact

I am trying to perform a readback (for the first time) from ISE (impact) on my Virtex II device. For some reason that f...
5 comments posted 21yrs
posted by sams235
5 comments posted 21yrs posted by sams235

Xilinx V4 Power Calculations

I am doing some evaluation on a possible XC4VFX20 design and had a question about the Xilinx Power Calculator on the we...
15 comments posted 21yrs
posted by JDDesignAndConsulting
15 comments posted 21yrs posted by JDDesignAndConsulting

WTB: Xilinx 6.2i EDK

Paying $200.00 mailto: snipped-for-privacy@starband.net
0 comments posted 21yrs
posted by tod.adamson
0 comments posted 21yrs posted by tod.adamson

Frequency Limit !!

Hi Everyone !! I was wondering about this stuff. Theoretically a 1:1 ratio between Processor and the PLB as well as bet...
1 comments posted 21yrs
posted by johnsons
1 comments posted 21yrs posted by johnsons

OPB Intc - HELP !!!!

I am writing the software for the PPC405 embedded in a V2pro. I have an OPB Intc Interrupt controller and am having tro...
1 comments posted 21yrs
posted by wesley.mowat
1 comments posted 21yrs posted by wesley.mowat

Reasonable Entry Level Dev. Board....

I am new to FPGA field, I took two classes, learning how to implemen multiplexers, shift registers, ALUs and pieces of...
1 comments posted 21yrs
posted by kg6lri
1 comments posted 21yrs posted by kg6lri

Virtex4 and ISE reality check?

I've heard a few painful stories about implementing Xilinx Virtex4 designs (bad SDF, bad bitfiles, power supply require...
6 comments posted 21yrs
posted by jjohnson
6 comments posted 21yrs posted by jjohnson

Microblaze FSL interface timing diagram

Hello Somehow I am not able to find in any Xilinx documentation a detail description of the FSL interface. I am especia...
1 comments posted 21yrs
posted by Patrick.Bateman23
1 comments posted 21yrs posted by Patrick.Bateman23

cross clock timing constraints

Hi all, Would appreciate a lot if i could get some help on this. Got a couple of questions and have read a lot of those...
4 comments posted 21yrs
posted by vasus_ss
4 comments posted 21yrs posted by vasus_ss

Cheap PowerPC G4 PCI coprocessor board for the PC

I am looking for the cheapest PowerPC G4 PCI coprocessor board for the PC. All boards I have found are for military/med...
1 comments posted 21yrs
posted by franciad
1 comments posted 21yrs posted by franciad