Latest threads in Field-Programmable Gate Arrays

JTAG without parallel port

I have a Xilinx Spartan 3 board, and comes only with the parallel JTAG cable. My big problem is that any of my computer...

3 21yrs

rafaelgonzalez

3 21yrs rafaelgonzalez

JTAG communication Problems in Quartus using Signal Tap

Hi newsgroup, I have got problems using Signal Tap with the Altera USB Blaster download cable. Sometimes the data colle...

8 21yrs

markus.knauss

8 21yrs markus.knauss

Re: Force sequential assigment

Hi, If you have the following code: if (count < 255) begin en_ram

0 21yrs

ann.lai

0 21yrs ann.lai

Force sequential assigment

Hi, If you have the following code: if (count < 255) begin en_ram

4 21yrs

ann.lai

4 21yrs ann.lai

200+ MHz through a SCSI cable

Hi, I am glad to tell you, that my LCD via LVDS works now :) However it works only up to a lvds clock rate of about 200...

9 21yrs

benjamin

9 21yrs benjamin

writing with impact to eeprom

Hi, I want to write my bitstream into the eeprom of my V2 Board. In my jtag chain in impact a xcf04s gets listed. Howev...

2 21yrs

benjamin

2 21yrs benjamin

Performing Readback from Impact

I am trying to perform a readback (for the first time) from ISE (impact) on my Virtex II device. For some reason that f...

5 21yrs

sams235

5 21yrs sams235

Xilinx V4 Power Calculations

I am doing some evaluation on a possible XC4VFX20 design and had a question about the Xilinx Power Calculator on the we...

15 21yrs

JDDesignAndConsulting

15 21yrs JDDesignAndConsulting

WTB: Xilinx 6.2i EDK

Paying $200.00 mailto: snipped-for-privacy@starband.net

0 21yrs

tod.adamson

0 21yrs tod.adamson

Frequency Limit !!

Hi Everyone !! I was wondering about this stuff. Theoretically a 1:1 ratio between Processor and the PLB as well as bet...

1 21yrs

johnsons

1 21yrs johnsons

OPB Intc - HELP !!!!

I am writing the software for the PPC405 embedded in a V2pro. I have an OPB Intc Interrupt controller and am having tro...

1 21yrs

wesley.mowat

1 21yrs wesley.mowat

Reasonable Entry Level Dev. Board....

I am new to FPGA field, I took two classes, learning how to implemen multiplexers, shift registers, ALUs and pieces of...

1 21yrs

kg6lri

1 21yrs kg6lri

Virtex4 and ISE reality check?

I've heard a few painful stories about implementing Xilinx Virtex4 designs (bad SDF, bad bitfiles, power supply require...

6 21yrs

jjohnson

6 21yrs jjohnson

Microblaze FSL interface timing diagram

Hello Somehow I am not able to find in any Xilinx documentation a detail description of the FSL interface. I am especia...

1 21yrs

Patrick.Bateman23

1 21yrs Patrick.Bateman23

cross clock timing constraints

Hi all, Would appreciate a lot if i could get some help on this. Got a couple of questions and have read a lot of those...

4 21yrs

vasus_ss

4 21yrs vasus_ss

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays