Max freq. of operation in FPGA?

PUNEET,

Gabor answered this question as well when you asked a slightly different question:

In summary, "before clock" numbers are purely delay. To reduce delay times, put FF's in your IOB's.

Have fun,

Marc

Hi marc, yes i asked somewhat same beforehand also. But just i got the doubt again.

Sorry i cud not understand putting FF's in IOB's to reduce delay.. can u explain further....... thanx in advance.......

I really meant to say "pushing FF's into the IOB", not putting *more* FF's there (although that might work as well, at the expense of an additional pipeline delay).

Here is a simplistic example of what we're talking about:

FF -> routing -> I/O pin

The delay figure in your report includes not just the I/O pin delay, but the routing delay all the way back to the FF that launches that signal. This routing delay can be significant (as your report indicates), and it can be variable, changing considerably from run to run of the tools. Now move the FF to the I/O pin:

routing -> FF -> I/O pin

Here, the routing delay is contrained by your clock period constraint. That means the only delay you have to worry about is the I/O pin delay, which is relatively small, and relatively fixed.

Peter just got finished trying to explain the input delay and FF's in another thread... perhaps reading that would help you understand why you want your do the same for your output:

Marc