I have a couple of questions regarding VHDL & synthesis for FPGA:
1) Are there any rule-of-thumb measurements for the max. no. of lines of code in a clocked process statement (I assume each extra code statement adds accumulated delays between successive clock edges) ?
2) Are there any good books that discuss issues relating to VHDL-FPGA synthesis i.e. exactly what code translates to & the various implications ?
1) If you have one clock edge driving 20,000 registers, all 20,000 registers can update at that clock edge. There is no direct penalty for having 2 registers versus 20k. The only limit on the number of lines in a clocked process statement is for your own readability, not the synthesizer's. Code statements don't add delay, complexity from register-to-register adds delay in "levels of logic" to implement the logical path. I can have one statement with enough complexity to force my maximum operating frequency into the single megahertz range and have a 1k line process that runs at 300 MHz.
2) Do you know how to design digital electronics? I'm talking registers, gates, memories, latches. Your best bet may be a text or course on basic digital electronics design to understand how logic is implemented independent of which language is used to model the logic. Once a solid understanding is had, the concept of parallelism versus the serial-native form of computer programming will become obvious.
Bad assumption - remember, VHDL is a hardware description language, not a programming language. What limits your timing is the path between flip-flops (usually through combinatorial logic). If each line defines a 'flop and a few levels of combinatorial logic feeding into another 'flop, then it doesn't really matter how many lines you have. Readability is nother question... :)
I've found some of the Xilinx techXclusives and app notes to be good in this regard - generally, coding style guidelines address this issue. I don't know of any books off hand, though no doubt other people on this NG will.
2) This is target specific as VHDL can be used on many different devices by several vendors. However, the book HDL Chip Design by Steven Smith shows schematics for all VHDL and Verilog examples. This will help you understand some concepts such as when latches are inferred and how case statements are dealt with but it won't help you optimize your design for a specific chip.