BlankHi, I seem to have a problem talking to a MAC chip that is connected as a memory mapped device on the EBI bus of an EPXA1-672 chip (EBI2 for CS, no split reads and no prefetch). EBI1 is connected to a flash chip. I am using the GNU toolset to develop code and no OS (as yet).
Apparently, if I read a single register (in my code), a series of 16 read accesses are made by the chip and cached. Subsequent reads do not access the MAC, rather return values from the cache - I do not see any CS transitions at the chip pins. The write operations function perfectly well if I do not perform a read - one CS for every write request. Once a read is performed, the writes also cease to be "executed" and change the register value in the cache only.
Has anyone seen a similar problem? The Altera folks have not responded to my trouble tickets - their support is not what it used to be.
Thanks, bta3