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Negative hold time from Quartus

Hi,

I am using Synplify Pro for synthesis and Qurtus for remaining steps. In my design , I am using the filp-flop output from a counter as the clock for few modules. While running the fitter it says .... Info: Promoted cell "Quadrature:Quadrature_Map|Quad_Clk_Div:Quad_Clk_Div_Map|dclk_intl_Z" to global signal automatically

But Later Timing Analizer says... Info: Detected ripple clock "Quadrature:Quadrature_Map|Quad_Clk_Div:Quad_Clk_Div_Map|dclk_intl_Z" as buffer Warning: Circuit may not operate. Detected 10 non-operational path(s) clocked by clock "Clk" with clock skew larger than data delay. See Compilation Report for details.

'dclk_intl' is a derived clock from 'Clk'.

and in the timing report I get all the sequential elements driven by dclk_intl as having negative hold time (Clock skew is more then the data dealy)

I searched this group and found related stuff. But that is for gated clock , and my clk source is from a sequential element.More over fitter promtes as making it a global signal but later I get a different message from timing analizer.

Please suggest to fix this ....

Thank you.

-- Mohammed A Khader.

Reply to
Mohammed A Khader
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In general while it might take a bit more time and thinking it is much more easier for the tolls as well as for your design to use instead of the counter result as clock to use it as clock enable

For example instead of

reg [1:0] cnt; always @ (posedge clk... ... cnt

Reply to
Berty

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