Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

including components, i.e. SRL16

Hi, when I want to use a SRL16, I have to "include" the component in my entity like this: component SRL16 port ( Q : ou...
6 comments posted 21yrs
posted by benjamin
6 comments posted 21yrs posted by benjamin

DVI implementation

I wonder if DVI can be implemented on an FPGA fabric - I mean receiver and transmitter. Some concerns I have: I/O cell T...
6 comments posted 21yrs
posted by lb.edc
6 comments posted 21yrs posted by lb.edc

Clock Gating

So, it seems from another thread that the general consensus is somewhat against clock gating. I'm still somewhat new at...
3 comments posted 21yrs
posted by rgaddi
3 comments posted 21yrs posted by rgaddi

VIIPro on-chip LVDS termination

As I understand it, the VIIPro devices have on-chip differential termination resistors which can be brought into play b...
3 comments posted 21yrs
posted by enquiries
3 comments posted 21yrs posted by enquiries

MicroBlaze latencies

In "Embedded System Tools Guide" on EDK6.2 say: ".... MicroBlaze requires 2 clock cycles to access on-chip Block RAM co...
0 comments posted 21yrs
posted by pi
0 comments posted 21yrs posted by pi

Xilinx Prom programming

I'm working with a Xilinx board (Spartan XC3S2000) and I can't program Flash Eprom. I'm using iMPACT software. I have g...
2 comments posted 21yrs
posted by zkwjy
2 comments posted 21yrs posted by zkwjy

how to constrain this

Hi, my pad input clock is 100 MHz (clk_ibufg). I have constrained this to period 10 ns. How should I constrain the lvds...
9 comments posted 21yrs
posted by benjamin
9 comments posted 21yrs posted by benjamin

Altera SDRam ip core

Hello, I interface my Cyclone with a micron SDRam using the Altera SDR SDRAM Controller but it seems that there is some...
0 comments posted 21yrs
posted by no-email
0 comments posted 21yrs posted by no-email

How to add DCM as customized IP using FSL channel

Hi All: I am trying to add my custmozied IP with DCM module in it using FSL channel. I am facing problem adding DCM mod...
0 comments posted 21yrs
posted by aroutchelvame
0 comments posted 21yrs posted by aroutchelvame

Help

Hallo, where I could find a complete manual (pdf) for programming in Ansi C? I need to understand the meaning of operato...
1 comments posted 21yrs
posted by marcotoschi_no_spam
1 comments posted 21yrs posted by marcotoschi_no_spam

Does this group allow JobPostings?

I am a senior technical recruiter with a very reputable firm, Common Agenda. I have postitions to post in the SF Bay Ar...
8 comments posted 21yrs
posted by eellsworth
8 comments posted 21yrs posted by eellsworth

Newbie VHDL/FPGA question

Hi, I have a couple of questions regarding VHDL & synthesis for FPGA: 1) Are there any rule-of-thumb measurements for t...
4 comments posted 21yrs
posted by dave_baker_100
4 comments posted 21yrs posted by dave_baker_100