including components, i.e. SRL16

Uncomment the following lines which ISE should insert in the beginning of any VHDL file it creates when you ask it to create a new "VHDL module":

library UNISIM; use UNISIM.VComponents.all;

This should allow you to use all the primitives defined in the Libraries Guide.

-Jim

Benjamin,

You can simply include the UNISIM library which contains the component declarations and attributes (black box attributes) for all of our supported components. I have included a simple example below that shows the instantiation of two SRLC16E's and a MUXF5 to produce a dynamic addressed,

Cheers... Mark Xilinx FAE

------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM; use UNISIM.VComponents.all;

entity srl16e_instance is PORT ( clk : in std_logic; ce : in std_logic; din : in std_logic; addr : in std_logic_vector(4 downto 0); dout : out std_logic ); end srl16e_instance;

architecture Behavioral of srl16e_instance is

signal srla : std_logic; -- output from U_SRL_LOW signal srlb : std_logic; -- output from U_SRL_HIGH signal srl_cascade : std_logic; -- cascade between LOW and HIGH

begin

u_SRL_LOW : SRLC16E generic map ( INIT => X"DEAD" ) port map ( CLK => clk, CE => ce, D => din, A0 => addr(0), A1 => addr(1), A2 => addr(2), A3 => addr(3), Q => srla, Q15 => srl_cascade );

u_SRL_HIGH : SRLC16E generic map ( INIT => X"BEEF" ) port map ( CLK => clk, CE => ce, D => srl_cascade, A0 => addr(0), A1 => addr(1), A2 => addr(2), A3 => addr(3), Q => srlb, Q15 => open );

mymux : MUXF5 port map ( I0 => srla, I1 => srlb, S => addr(4), O => dout );

end Behavioral;

Libraries Guide is always a good place to start for component instantiation. There are some component templates also available in ISE under the little light style button.

If you want a simple shift then doing it in VHDL or Verilog is also easy. If write your code as the following style (VHDL shown), i.e. without a reset, most synthesisers will turn it into SRL16 based logic.

process(clk) begin if clk'event and clk='1' then

shift1 when I want to use a SRL16, I have to "include" the component in my entity

Hi Jim,

Thanks, that was it.

regards, Benjamin

Yikes! I guess I don't know why you would write a shift register that way.

signal shift : std_logic_vector(n downto 0);

process(clk) begin if rising_edge(clk) then shift

I do when it's buses I am shifting. It is a single bit then I do use assignment and concatination.

John Adair Enterpo>> Libraries Guide is always a good place to start for component