Hi,
I know a little bit of the answer already by now. It is because, the DCM auto constraints were not there, before I added the clk constraint.
Is it possible to get the DCM auto constraints into the synthesize constraints? At the moment they are only in the Post and Place constraints, so synthesize doesn't optimize according to the DCM constraints.
Next question: My lvds clock runs at 360 MHz now. However the Hsync and Vsync logic only needs to be updated every 7 cycles. At the beginning (see upper post) I had errors, complaining that the logic wasn't fast enough. I knew that, therefore I start the hsync and vsync calculations in cycle
3, but I need them only in cycle 1 (it goes 0-1-2-3-4-5-6-0, the signal is called lvds_div). I have attached the process.
My solution is this: I have put all the col and row lines into a group, and set the from-to constraint to 5ns (equals about 2 lvds cycles).
INST "row_count_0" TNM = "sync_logic_grp"; ... INST "col_count_0" TNM = "sync_logic_grp"; ... TIMESPEC "TS_sync_logic_grp" = FROM "sync_logic_grp" TO "sync_logic_grp"
5 ns;
It would be nice to know, how a fpga veteran would do this, my methodology is probably not the best yet. Can I do something with a period constraint on the row and col signals?
My route process has become very slow after these constraints, it goes now up to phase 25. Is there a way to get it faster again?
Thanks for Your help!
regards, Benjamin
process (lvds_tick,screen_reset) begin if screen_reset='1' then col_count